eb8e8df92a
FSP has recently added support for a UPD switch to disable the non-GPU HD Audio controller. This change adds the coreboot side of the feature. To avoid having two HD Audio enable options, the value of the hd_audio_enable UPD is determined by the enable state of the non-GPU HD Audio controller in the platform devicetree. BUG=b:158535201,b:162302028 BRANCH=zork TEST=With the corresponding FSP change applied the non-GPU HD Audio device is hidden when switched off in devicetree and remains present and functional when switched on in devicetree. Change-Id: Ib2965e0742f4148e42a44ddad8ee05f0c4c7237e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44680 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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.. | ||
acpi | ||
bootblock | ||
include/soc | ||
psp_verstage | ||
acp.c | ||
acpi.c | ||
agesa_acpi.c | ||
aoac.c | ||
chip.c | ||
chip.h | ||
config.c | ||
cpu.c | ||
data_fabric.c | ||
dmi.c | ||
finalize.c | ||
fsp_params.c | ||
gpio.c | ||
graphics.c | ||
i2c.c | ||
Kconfig | ||
Makefile.inc | ||
mca.c | ||
memlayout.ld | ||
memlayout_psp_verstage.ld | ||
memlayout_x86.ld | ||
memmap.c | ||
mrc_cache.c | ||
pcie_gpp.c | ||
pmutil.c | ||
psp.c | ||
reset.c | ||
romstage.c | ||
root_complex.c | ||
sata.c | ||
smi.c | ||
smi_util.c | ||
smihandler.c | ||
smu.c | ||
soc_util.c | ||
southbridge.c | ||
tsc_freq.c | ||
uart.c | ||
uart_console.c | ||
update_microcode.c | ||
xhci.c |