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return that skipped the disable code. This patch removes the return and fixes the UART disable code. The problem was that the disable code was ORing bits into the Legacy_IO MSR causing issues with the LPC SIOs init code that would manifest as a hang because the IO would not be decoded correctly. ANDing to clear the bits fixes the issue. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 |
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| .. | ||
| arch | ||
| boot | ||
| config | ||
| console | ||
| cpu | ||
| devices | ||
| drivers | ||
| include | ||
| lib | ||
| mainboard | ||
| northbridge | ||
| pc80 | ||
| pmc/altimus/mpc7410 | ||
| ram | ||
| sdram | ||
| southbridge | ||
| stream | ||
| superio | ||