6d19a20f5f
Field 'OEMID' & "OEM Table ID" are related to DSDT table not to mainboard. So use macro to set them respectvely to "COREv4" and "COREBOOT". Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
83 lines
2.2 KiB
Text
83 lines
2.2 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <variant/ec.h>
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/* DefinitionBlock Statement */
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#include <arch/acpi.h>
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DefinitionBlock (
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"DSDT.AML", /* Output filename */
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"DSDT", /* Signature */
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0x02, /* DSDT Revision, needs to be 2 for 64bit */
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x00010001 /* OEM Revision */
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)
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{ /* Start of ASL file */
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/* #include <arch/x86/acpi/debug.asl> */ /* as needed */
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/* global NVS and variables */
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#include <globalnvs.asl>
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/* Globals for the platform */
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#include <variant/acpi/mainboard.asl>
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/* PCI IRQ mapping for the Southbridge */
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#include <pcie.asl>
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/* Describe the processor tree (\_PR) */
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#include <cpu.asl>
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/* Contains the supported sleep states for this chipset */
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#include <sleepstates.asl>
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/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
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#include <variant/acpi/sleep.asl>
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/* Contains _SWS methods */
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#include <acpi_wake_source.asl>
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/* System Bus */
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Scope(\_SB) { /* Start \_SB scope */
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/* global utility methods expected within the \_SB scope */
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#include <arch/x86/acpi/globutil.asl>
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/* IRQ Routing mapping for this platform (in \_SB scope) */
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#include <variant/acpi/routing.asl>
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/* Describe the SOC */
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#include <soc.asl>
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} /* End \_SB scope */
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/* Thermal handler */
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#include <variant/acpi/thermal.asl>
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/* Chrome OS specific */
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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/* Chrome OS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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/* Define the General Purpose Events for the platform */
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#include <variant/acpi/gpe.asl>
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}
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/* End of ASL file */
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