coreboot-kgpe-d16/src/northbridge/intel
Arthur Heymans f1287266ab nb/intel/x4x: Add DDR3 JEDEC init
Add DDR3 JEDEC init (Power up and Initialization by setting emrs regs)

This also modifies the send_jedec_cmd function as DDR3 dimms can have
ranks mirrored which needs to be accounted for.

The ddr3_emrs1_config array is placed externally since it is also
needed for write leveling.

Change-Id: I510b8669aaa48ba99fb4dcf1ece716aef26741bb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-24 13:03:15 +00:00
..
e7505 nb/intel/e7505: Get rid of device_t 2018-05-18 12:17:54 +00:00
fsp_rangeley {mb,nb,soc}: Remove references to pci_bus_default_ops() 2018-05-08 03:01:04 +00:00
fsp_sandybridge nb/intel/fsp_sandybridge: Get rid of device_t 2018-05-14 22:26:24 +00:00
gm45 {mb,nb,soc}: Remove references to pci_bus_default_ops() 2018-05-08 03:01:04 +00:00
haswell nb/intel/haswell: Get rid of device_t 2018-05-18 12:17:43 +00:00
i440bx nb/intel/i440bx: Get rid of device_t 2018-05-11 09:02:55 +00:00
i945 nb/intel/i945/raminit.c: Remove not necessary braces {} 2018-05-14 22:25:02 +00:00
nehalem nb/intel/nehalem: Fix smashed stack in romstage 2018-05-21 13:25:24 +00:00
pineview {mb,nb,soc}: Remove references to pci_bus_default_ops() 2018-05-08 03:01:04 +00:00
sandybridge nb/intel/sandybridge: Get rid of device_t 2018-05-24 10:36:37 +00:00
x4x nb/intel/x4x: Add DDR3 JEDEC init 2018-05-24 13:03:15 +00:00