086730b062
Skylake Core boot should have configurable option to skip PCH based SD 3.0 Controller from customer/reference design. Addition to that no unused or unnecessary should list under device view. BUG=chrome-os-partner:48190 BRANCH=None TEST=Build & boot Kunimitsu and LARs. Change-Id: Ie17fd6db01e0cabcdf605017509d809b54509a0d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 99ac17b723125822368539d0562aa35119e520fb Original-Change-Id: I98a48f45ef442246227fd54ea021b53f824954c5 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315420 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12946 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> |
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.. | ||
dptf | ||
cpu.asl | ||
globalnvs.asl | ||
gpio.asl | ||
irqlinks.asl | ||
lpc.asl | ||
pch.asl | ||
pch_hda.asl | ||
pci_irqs.asl | ||
pcie.asl | ||
pcr.asl | ||
platform.asl | ||
pmc.asl | ||
scs.asl | ||
serialio.asl | ||
sleepstates.asl | ||
smbus.asl | ||
systemagent.asl | ||
xhci.asl |