Philipp Hug 2326a284ac riscv: add trampoline in MBR block to support boot mode 1 ... Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock. Tested on hardware: boot mode 15: works as before boot mode 1: jump to bootblock works, but bootblock needs to be modified to move the stack to L2LIM. This will be in a separate commit. Further changes are needed in the bootblock Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>		2018-09-14 14:33:09 +00:00
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description.md	util: Add description.md to each util	2018-07-26 13:26:50 +00:00
make-spike-elf.sh	…
sifive-gpt.py	riscv: add trampoline in MBR block to support boot mode 1	2018-09-14 14:33:09 +00:00
spike-elf.ld	util/riscvtools: Rename to util/riscv/	2018-04-25 11:43:20 +00:00