4a0899fe52
Change-Id: I67de5260a756fc7b1cf0ec1903bee0058a2dcb06 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
50 lines
1.4 KiB
C
50 lines
1.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef DCP847SKE_SUPERIO_H
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#define DCP847SKE_SUPERIO_H
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#include <arch/io.h>
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#include <superio/hwm5_conf.h>
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#define NUVOTON_PORT 0x4e
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#define HWM_PORT 0x0a30
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#define GPIO_PORT 0x0a80
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#define SUPERIO_BANK(x) (0x0700 | x)
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#define SUPERIO_INITVAL(reg, data) ((reg << 8) | (data))
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#define HWM_BANK(x) (0x4e00 | x)
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#define HWM_INITVAL SUPERIO_INITVAL
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#define SUPERIO_UNLOCK do { \
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outb(0x87, NUVOTON_PORT); \
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outb(0x87, NUVOTON_PORT); \
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} while (0)
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#define SUPERIO_LOCK do { \
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outb(0xaa, NUVOTON_PORT); \
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} while (0)
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#define SUPERIO_WRITE(reg, data) do { \
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outb((reg), NUVOTON_PORT); \
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outb((data), NUVOTON_PORT + 1); \
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} while (0)
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#define SUPERIO_WRITE_INITVAL(val) SUPERIO_WRITE((val) >> 8, (val) & 0xff)
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#define HWM_WRITE_INITVAL(val) pnp_write_hwm5_index(HWM_PORT, (val) >> 8, (val) & 0xff)
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#endif /* DCP847SKE_SUPERIO_H */
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