Kerry Sheh f3b0500050 SB800: Hide unused gpp ports ... Add configure option SB_GPP_UNHIDE_PORTS for mainboard to hide/unhide the unused sb800 gpp ports. Certain gpp port should be hidden, if no device was detected and hotplug feature is disabled for such port. Hidden unused ports makes lspci -vvv get more accurate information under Linux. Test on avalue/eax-785e mainboard. Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>		2011-10-23 14:08:20 +02:00
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arch/x86	Extend coreboot table entry for serial ports	2011-10-21 23:34:30 +02:00
boot	Use ntohll where appropriate.	2011-10-21 14:14:32 +02:00
console	Extend coreboot table entry for serial ports	2011-10-21 23:34:30 +02:00
cpu	Activate older Xeon P4 microcodes	2011-10-18 00:10:51 +02:00
devices	Use ntohll where appropriate.	2011-10-21 14:14:32 +02:00
drivers	sconfig: check whether component directory actually exists	2011-10-19 03:31:21 +02:00
ec	T60: Add support for Ultrabay Legacy I/O devices (40Y8122)	2011-10-20 16:06:35 +02:00
include	Extend coreboot table entry for serial ports	2011-10-21 23:34:30 +02:00
lib	Use ntohll where appropriate.	2011-10-21 14:14:32 +02:00
mainboard	SB800: Hide unused gpp ports	2011-10-23 14:08:20 +02:00
northbridge	I945: replace #if defined() by #if	2011-10-19 00:09:23 +02:00
pc80	Fix our CMOS checksum algorithm so it matches what /dev/nvram expects	2011-10-17 17:51:52 +02:00
southbridge	SB800: Hide unused gpp ports	2011-10-23 14:08:20 +02:00
superio	Append logical PME/GPIO device. Fix MPU device number.	2011-10-18 00:11:33 +02:00
vendorcode	Fix AMD SB800 (cimx) southbridge code to compile with gcc 4.6	2011-10-14 22:57:11 +02:00
Kconfig	refactor vesa mode setting code and bootsplash code	2011-10-13 20:00:50 +02:00
Kconfig.deprecated_options	some ifdef --> if fixes	2011-04-21 20:24:43 +00:00