0fb58f32c4
These parameters are not used and not necessary in sdram.c, because the DDR PLL is configured in clock.c. Change-Id: I8060bd21e05765cedf7bdabc28052c32774f9ca1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28710 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
67 lines
1.9 KiB
C
67 lines
1.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Philipp Hug <philipp@hug.cx>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/sdram.h>
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#include <soc/addressmap.h>
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#include "regconfig-phy.h"
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#include "regconfig-ctl.h"
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#include "ux00ddr.h"
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#define DENALI_PHY_DATA ddr_phy_settings
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#define DENALI_CTL_DATA ddr_ctl_settings
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#include "ddrregs.h"
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#define DDR_SIZE (8UL * 1024UL * 1024UL * 1024UL)
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void sdram_init(void)
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{
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ux00ddr_writeregmap(FU540_DDRCTRL, ddr_ctl_settings, ddr_phy_settings);
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ux00ddr_disableaxireadinterleave(FU540_DDRCTRL);
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ux00ddr_disableoptimalrmodw(FU540_DDRCTRL);
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ux00ddr_enablewriteleveling(FU540_DDRCTRL);
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ux00ddr_enablereadleveling(FU540_DDRCTRL);
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ux00ddr_enablereadlevelinggate(FU540_DDRCTRL);
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if (ux00ddr_getdramclass(FU540_DDRCTRL) == DRAM_CLASS_DDR4)
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ux00ddr_enablevreftraining(FU540_DDRCTRL);
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//mask off interrupts for leveling completion
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ux00ddr_mask_leveling_completed_interrupt(FU540_DDRCTRL);
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ux00ddr_mask_mc_init_complete_interrupt(FU540_DDRCTRL);
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ux00ddr_mask_outofrange_interrupts(FU540_DDRCTRL);
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ux00ddr_setuprangeprotection(FU540_DDRCTRL, DDR_SIZE);
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ux00ddr_mask_port_command_error_interrupt(FU540_DDRCTRL);
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const uint64_t ddr_size = DDR_SIZE;
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const uint64_t ddr_end = FU540_DRAM + ddr_size;
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ux00ddr_start(FU540_DDRCTRL, FU540_DDRBUSBLOCKER, ddr_end);
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ux00ddr_phy_fixup(FU540_DDRCTRL);
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}
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size_t sdram_size_mb(void)
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{
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static size_t size_mb = 0;
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if (!size_mb) {
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// TODO: implement
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size_mb = 8 * 1024;
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}
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return size_mb;
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}
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