9cbc90a1f6
All mainboards (nyans) utilizing the cache_policy option has it set to DCACHE_WRITETHROUGH. This option is for setting the framebuffer's cache attribute. However, this option is reliant on an architecture-specific enumeration. Just remove the option and use DCACHE_WRITETHROUGH across the board. If someone wants to reconfigure it at a later date one can introduce a non-architecture specific option. Change-Id: I6a0848231f5e28d36ec2d56b239bed67619fe5a7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15838 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
88 lines
2.9 KiB
Text
88 lines
2.9 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright 2014 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip soc/nvidia/tegra124
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device cpu_cluster 0 on end
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# N.B. We ae not using the device tree in an effective way.
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# We need to change this in future such that the on-soc
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# devices are 'chips', which will allow us to go at them
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# in parallel. This is even easier on the ARM SOCs since there
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# are no single-access resources such as the infamous
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# cf8/cfc registers found on PCs.
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register "display_controller" = "TEGRA_ARM_DISPLAYA"
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register "xres" = "1366"
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register "yres" = "768"
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# bits per pixel and color depth
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register "framebuffer_bits_per_pixel" = "16"
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register "color_depth" = "6"
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# "6" is defined as COLOR_DEPTH_B5G6R5 in dc_reg.h
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register "panel_bits_per_pixel" = "18"
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# With some help from the mainbaord designer
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register "backlight_en_gpio" = "GPIO(H2)"
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register "lvds_shutdown_gpio" = "0"
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register "backlight_vdd_gpio" = "GPIO(P2)"
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register "panel_vdd_gpio" = "0"
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register "pwm" = "1"
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# various panel delay time
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register "vdd_delay_ms" = "200"
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register "pwm_to_bl_delay_ms" = "10"
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register "vdd_to_hpd_delay_ms" = "200"
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register "hpd_unplug_min_us" = "2000"
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register "hpd_plug_min_us" = "250"
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register "hpd_irq_min_us" = "250"
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# How to compute these: xrandr --verbose will give you this:
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#Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm
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# 2560 2608 2640 2720 hborder 0
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# 1700 1703 1713 1749 vborder 0
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#Then you can compute your values:
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#H front porch = 2608 - 2560 = 48
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#H sync = 2640 - 2608 = 32
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#H back porch = 2720 - 2640 = 80
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#V front porch = 1703 - 1700 = 3
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#V sync = 1713 - 1703 = 10
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#V back porch = 1749 - 1713 = 36
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#href_to_sync and vref_to_sync are from the vendor
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#this is just an example for a Pixel panel; other panels differ.
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# Here is a peppy panel:
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# 1366x768 (0x45) 76.4MHz -HSync -VSync *current +preferred
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# h: width 1366 start 1502 end 1532 total 1592
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# v: height 768 start 776 end 788 total 800
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register "href_to_sync" = "1"
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register "hfront_porch" = "136"
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register "hsync_width" = "30"
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register "hback_porch" = "60"
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register "vref_to_sync" = "1"
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register "vfront_porch" = "8"
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register "vsync_width" = "12"
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register "vback_porch" = "12"
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register "pixel_clock" = "76400000"
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# link configurations
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register "lane_count" = "1"
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register "enhanced_framing" = "1"
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register "link_bw" = "10"
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# "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h
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register "drive_current" = "0x40404040"
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register "preemphasis" = "0x0f0f0f0f"
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register "postcursor" = "0"
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end
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