coreboot-kgpe-d16/src/soc/rockchip/rk3288
Julius Werner f8dcdea609 rk3288: Fix some PLL divisors and improve clock code
This patch does some general cleanup in the Rockchip clock code, and
adds some more assertions regarding the PLL VCO and output frequency
ranges. It changes all PLL divisors to use the lowest values that can
still hit the target frequency, since higher NR values lead to higher
jitter and higher NO values increase power draw.

Also change DDR3 frequency code to hardcode the optimal divisors for
certail frequencies. As a little hack we will interpret 666000000 to
actually mean 666666666.6P (and analogous for 533MHz), since that's what
you usually want for memory.

BUG=chrome-os-partner:32139
TEST=Boot on veyron_pinky rev2, check that dpll_is shown as 666666666 in
/sys/kernel/debug/clk/clk_summary.

Change-Id: I57d7ef34500984184e010c0cc7d73789338834d4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7466ffc035b3f06ac280f412bc496059abf3239c
Original-Change-Id: I4f3c39641955a95c6dfbe9334035eb670b138bf0
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/221801
Reviewed-on: http://review.coreboot.org/9339
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-08 08:48:03 +02:00
..
addressmap.h
bootblock.c pinky: Move some init to mainboard bootblock 2015-04-02 23:27:36 +02:00
cbmem.c rk3288: update romstage & mainboard 2015-03-24 15:25:31 +01:00
chip.h veyron: Fix file permissions 2015-03-24 15:25:35 +01:00
clock.c rk3288: Fix some PLL divisors and improve clock code 2015-04-08 08:48:03 +02:00
clock.h rk3288: set cpu frequency up to 1.8GHz 2015-04-04 15:05:12 +02:00
gpio.c veyron: Fix file permissions 2015-03-24 15:25:35 +01:00
gpio.h rk3288: Add GPIO() macro 2015-03-27 08:06:51 +01:00
grf.h rockchip: support pwm regulator 2015-04-02 21:16:45 +02:00
i2c.c rk3288: guarantee i2c low period more than 1.3us 2015-04-04 15:04:39 +02:00
i2c.h rockchip: support i2c clock setting 2015-04-02 21:16:28 +02:00
Kconfig New mechanism to define SRAM/memory map with automatic bounds checking 2015-04-06 22:05:01 +02:00
Makefile.inc rk3288: set cpu frequency up to 1.8GHz 2015-04-04 15:05:12 +02:00
media.c New mechanism to define SRAM/memory map with automatic bounds checking 2015-04-06 22:05:01 +02:00
memlayout.ld New mechanism to define SRAM/memory map with automatic bounds checking 2015-04-06 22:05:01 +02:00
monotonic_timer.c
pmu.h rk3288: add iomux operation 2015-03-24 15:24:31 +01:00
pwm.c rockchip: support pwm regulator 2015-04-02 21:16:45 +02:00
pwm.h rockchip: support pwm regulator 2015-04-02 21:16:45 +02:00
rk808.c rk3288: set cpu frequency up to 1.8GHz 2015-04-04 15:05:12 +02:00
rk808.h rk3288: set cpu frequency up to 1.8GHz 2015-04-04 15:05:12 +02:00
sdram.c veyron_pinky/rk3288: Use KHz, MHz and GHz constants 2015-04-04 15:02:24 +02:00
sdram.h rk3288: add ddr driver 2015-03-24 15:25:23 +01:00
soc.c rk3288: add cpu and chip 2015-03-24 15:25:27 +01:00
soc.h New mechanism to define SRAM/memory map with automatic bounds checking 2015-04-06 22:05:01 +02:00
spi.c rk3288: Re-write spi_xfer() to support full duplex 2015-04-08 08:47:57 +02:00
spi.h rk3288: Pass SPI bus speed in as parameter to init function 2015-04-04 04:03:18 +02:00
timer.c veyron_pinky/rk3288: Use KHz, MHz and GHz constants 2015-04-04 15:02:24 +02:00
timer.h rk3288: Fix some PLL divisors and improve clock code 2015-04-08 08:48:03 +02:00
uart.c