fa6014a6ec
This is to match the layout of the non-fsp baytrail to make comparisons easier and possibly remove duplicate files. Change-Id: I9a94842d724ab3826de711d398227e7bdc1045ff Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12686 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
82 lines
2.5 KiB
C
82 lines
2.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef IRQROUTE_H
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#define IRQROUTE_H
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#include <soc/intel/fsp_baytrail/include/soc/irq.h>
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#include <soc/intel/fsp_baytrail/include/soc/pci_devs.h>
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/*
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*IR02h GFX INT(A) - PIRQ A
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*IR10h EMMC INT(ABCD) - PIRQ DEFG
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*IR11h SDIO INT(A) - PIRQ B
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*IR12h SD INT(A) - PIRQ C
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*IR13h SATA INT(A) - PIRQ D
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*IR14h XHCI INT(A) - PIRQ E
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*IR15h LP Audio INT(A) - PIRQ F
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*IR17h MMC INT(A) - PIRQ F
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*IR18h SIO INT(ABCD) - PIRQ BADC
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*IR1Ah TXE INT(A) - PIRQ F
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*IR1Bh HD Audio INT(A) - PIRQ G
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*IR1Ch PCIe INT(ABCD) - PIRQ EFGH
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*IR1Dh EHCI INT(A) - PIRQ D
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*IR1Eh SIO INT(ABCD) - PIRQ BDEF
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*IR1Fh LPC INT(ABCD) - PIRQ HGBC
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*/
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/* PCIe bridge routing */
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#define BRIDGE1_DEV PCIE_DEV
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/* PCI bridge IRQs need to be updated in both tables and need to match */
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#define PCIE_BRIDGE_IRQ_ROUTES \
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PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H)
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/* Devices set as A, A, A, A evaluate as 0, and don't get set */
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#define PCI_DEV_PIRQ_ROUTES \
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PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \
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PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
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PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
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PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \
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PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \
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PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
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/*
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* Route each PIRQ[A-H] to a PIC IRQ[0-15]
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* Reserved: 0, 1, 2, 8, 13
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* PS2 keyboard: 12
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* ACPI/SCI: 9
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* Floppy: 6
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*/
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#define PIRQ_PIC_ROUTES \
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PIRQ_PIC(A, 4), \
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PIRQ_PIC(B, 5), \
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PIRQ_PIC(C, 7), \
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PIRQ_PIC(D, 10), \
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PIRQ_PIC(E, 11), \
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PIRQ_PIC(F, 12), \
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PIRQ_PIC(G, 14), \
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PIRQ_PIC(H, 15)
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#endif /* IRQROUTE_H */
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