intel/fsp_baytrail: rename include folder baytrail to include/soc

This is to match the layout of the non-fsp baytrail to make comparisons
easier and possibly remove duplicate files.

Change-Id: I9a94842d724ab3826de711d398227e7bdc1045ff
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12686
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

src/mainboard/esd/atom15/acpi_tables.c

@@ -28,9 +28,9 @@
 #include <device/pci_ids.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
-#include <baytrail/acpi.h>
-#include <baytrail/nvs.h>
-#include <baytrail/iomap.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include <soc/iomap.h>
 
 void acpi_create_gnvs(global_nvs_t *gnvs)
 {

src/mainboard/esd/atom15/fadt.c

@@ -15,7 +15,7 @@
  */
 
 #include <arch/acpi.h>
-#include <baytrail/acpi.h>
+#include <soc/acpi.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {

src/mainboard/esd/atom15/gpio.c

@@ -15,7 +15,7 @@
  */
 
 #include <stdlib.h>
-#include <baytrail/gpio.h>
+#include <soc/gpio.h>
 #include "irqroute.h"
 
 /*

src/mainboard/esd/atom15/irqroute.h

@@ -17,8 +17,8 @@
 #ifndef IRQROUTE_H
 #define IRQROUTE_H
 
-#include <soc/intel/fsp_baytrail/baytrail/irq.h>
-#include <soc/intel/fsp_baytrail/baytrail/pci_devs.h>
+#include <soc/intel/fsp_baytrail/include/soc/irq.h>
+#include <soc/intel/fsp_baytrail/include/soc/pci_devs.h>
 
 /*
  *IR02h GFX      INT(A) 	- PIRQ A

src/mainboard/esd/atom15/romstage.c

@@ -15,12 +15,12 @@
  * GNU General Public License for more details.
  */
 
-#include <baytrail/romstage.h>
+#include <soc/romstage.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include <baytrail/gpio.h>
-#include "chip.h"
+#include <soc/gpio.h>
+#include <soc/intel/fsp_baytrail/chip.h>
 
 /**
  * /brief mainboard call for setup that needs to be done before fsp init

src/mainboard/intel/bayleybay_fsp/acpi_tables.c

@@ -27,9 +27,9 @@
 #include <device/pci_ids.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
-#include <baytrail/acpi.h>
-#include <baytrail/nvs.h>
-#include <baytrail/iomap.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include <soc/iomap.h>
 
 void acpi_create_gnvs(global_nvs_t *gnvs)
 {

src/mainboard/intel/bayleybay_fsp/fadt.c

@@ -15,7 +15,7 @@
  */
 
 #include <arch/acpi.h>
-#include <baytrail/acpi.h>
+#include <soc/acpi.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {

src/mainboard/intel/bayleybay_fsp/gpio.c

@@ -15,7 +15,7 @@
  */
 
 #include <stdlib.h>
-#include <baytrail/gpio.h>
+#include <soc/gpio.h>
 #include "irqroute.h"
 
 /* NCORE GPIOs */

src/mainboard/intel/bayleybay_fsp/irqroute.h

@@ -16,8 +16,8 @@
 #ifndef IRQROUTE_H
 #define IRQROUTE_H
 
-#include <soc/intel/fsp_baytrail/baytrail/irq.h>
-#include <soc/intel/fsp_baytrail/baytrail/pci_devs.h>
+#include <soc/intel/fsp_baytrail/include/soc/irq.h>
+#include <soc/intel/fsp_baytrail/include/soc/pci_devs.h>
 
 /*
  *IR02h GFX      INT(A) 	- PIRQ A

src/mainboard/intel/bayleybay_fsp/romstage.c

@@ -25,13 +25,13 @@
 #include <cpu/x86/mtrr.h>
 #include <romstage_handoff.h>
 #include <timestamp.h>
-#include <baytrail/gpio.h>
-#include <baytrail/iomap.h>
-#include <baytrail/lpc.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/romstage.h>
-#include <baytrail/acpi.h>
-#include <baytrail/baytrail.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+#include <soc/acpi.h>
+#include <soc/baytrail.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>
 
 /**

src/mainboard/intel/minnowmax/acpi_tables.c

@@ -28,9 +28,9 @@
 #include <device/pci_ids.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
-#include <baytrail/acpi.h>
-#include <baytrail/nvs.h>
-#include <baytrail/iomap.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include <soc/iomap.h>
 
 void acpi_create_gnvs(global_nvs_t *gnvs)
 {

src/mainboard/intel/minnowmax/fadt.c

@@ -15,7 +15,7 @@
  */
 
 #include <arch/acpi.h>
-#include <baytrail/acpi.h>
+#include <soc/acpi.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {

src/mainboard/intel/minnowmax/gpio.c

@@ -15,7 +15,7 @@
  */
 
 #include <stdlib.h>
-#include <baytrail/gpio.h>
+#include <soc/gpio.h>
 #include "irqroute.h"
 
 /*

src/mainboard/intel/minnowmax/irqroute.h

@@ -17,8 +17,8 @@
 #ifndef IRQROUTE_H
 #define IRQROUTE_H
 
-#include <soc/intel/fsp_baytrail/baytrail/irq.h>
-#include <soc/intel/fsp_baytrail/baytrail/pci_devs.h>
+#include <soc/intel/fsp_baytrail/include/soc/irq.h>
+#include <soc/intel/fsp_baytrail/include/soc/pci_devs.h>
 
 /*
  *IR02h GFX      INT(A) 	- PIRQ A

src/mainboard/intel/minnowmax/romstage.c

@@ -15,12 +15,12 @@
  * GNU General Public License for more details.
  */
 
-#include <baytrail/romstage.h>
+#include <soc/romstage.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include <baytrail/gpio.h>
-#include "chip.h"
+#include <soc/gpio.h>
+#include <soc/intel/fsp_baytrail/chip.h>
 
 /**
  * /brief mainboard call for setup that needs to be done before fsp init

src/mainboard/siemens/mc_tcu3/acpi_tables.c

@@ -27,9 +27,9 @@
 #include <device/pci_ids.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
-#include <baytrail/acpi.h>
-#include <baytrail/nvs.h>
-#include <baytrail/iomap.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include <soc/iomap.h>
 
 void acpi_create_gnvs(global_nvs_t *gnvs)
 {

src/mainboard/siemens/mc_tcu3/fadt.c

@@ -15,7 +15,7 @@
  */
 
 #include <arch/acpi.h>
-#include <baytrail/acpi.h>
+#include <soc/acpi.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {

src/mainboard/siemens/mc_tcu3/gpio.c

@@ -15,7 +15,7 @@
  */
 
 #include <stdlib.h>
-#include <baytrail/gpio.h>
+#include <soc/gpio.h>
 #include "irqroute.h"
 
 /* NCORE GPIOs */

src/mainboard/siemens/mc_tcu3/irqroute.h

@@ -16,8 +16,8 @@
 #ifndef IRQROUTE_H
 #define IRQROUTE_H
 
-#include <soc/intel/fsp_baytrail/baytrail/irq.h>
-#include <soc/intel/fsp_baytrail/baytrail/pci_devs.h>
+#include <soc/intel/fsp_baytrail/include/soc/irq.h>
+#include <soc/intel/fsp_baytrail/include/soc/pci_devs.h>
 
 /*
  *IR02h GFX      INT(A) 	- PIRQ A

src/mainboard/siemens/mc_tcu3/lcd_panel.c

@@ -16,7 +16,7 @@
 #include <console/console.h>
 #include <string.h>
 #include "modhwinfo.h"
-#include "baytrail/gpio.h"
+#include "soc/gpio.h"
 #include "lcd_panel.h"
 #include "ptn3460.h"
 

src/mainboard/siemens/mc_tcu3/ptn3460.c

@@ -14,7 +14,7 @@
  */
 
 #include <console/console.h>
-#include "baytrail/i2c.h"
+#include "soc/i2c.h"
 #include "ptn3460.h"
 
 /** \brief This functions sets up the DP2LVDS-converter to be used with the

src/mainboard/siemens/mc_tcu3/romstage.c

@@ -25,13 +25,13 @@
 #include <cpu/x86/mtrr.h>
 #include <romstage_handoff.h>
 #include <timestamp.h>
-#include <baytrail/gpio.h>
-#include <baytrail/iomap.h>
-#include <baytrail/lpc.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/romstage.h>
-#include <baytrail/acpi.h>
-#include <baytrail/baytrail.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+#include <soc/acpi.h>
+#include <soc/baytrail.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>
 #include "modhwinfo.h"
 

src/soc/intel/fsp_baytrail/Makefile.inc

@@ -55,7 +55,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
 ramstage-y += placeholders.c
 ramstage-y += i2c.c
 
-CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/
+CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
 
 endif

src/soc/intel/fsp_baytrail/acpi.c

@@ -28,21 +28,21 @@
 #include <arch/smp/mpspec.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <baytrail/baytrail.h>
+#include <soc/baytrail.h>
 #include <device/pci_ids.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/acpi.h>
+#include <soc/pci_devs.h>
+#include <soc/acpi.h>
 #include <string.h>
-#include <baytrail/iomap.h>
-#include <baytrail/lpc.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/irq.h>
-#include <baytrail/iosf.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/irq.h>
+#include <soc/iosf.h>
 #include <arch/io.h>
-#include <baytrail/msr.h>
-#include <baytrail/pattrs.h>
-#include <baytrail/pmc.h>
+#include <soc/msr.h>
+#include <soc/pattrs.h>
+#include <soc/pmc.h>
 #include <cpu/cpu.h>
 #include <cbmem.h>
 

src/soc/intel/fsp_baytrail/acpi/gpio.asl

@@ -14,8 +14,8 @@
  * GNU General Public License for more details.
  */
 
-#include <soc/intel/fsp_baytrail/baytrail/iomap.h>
-#include <soc/intel/fsp_baytrail/baytrail/irq.h>
+#include <soc/intel/fsp_baytrail/include/soc/iomap.h>
+#include <soc/intel/fsp_baytrail/include/soc/irq.h>
 
 /* SouthCluster GPIO */
 Device (GPSC)

src/soc/intel/fsp_baytrail/acpi/southcluster.asl

@@ -14,9 +14,9 @@
  * GNU General Public License for more details.
  */
 
-#include <soc/intel/fsp_baytrail/baytrail/iomap.h>
-#include <soc/intel/fsp_baytrail/baytrail/irq.h>
-#include "../baytrail/baytrail.h"
+#include <soc/intel/fsp_baytrail/include/soc/iomap.h>
+#include <soc/intel/fsp_baytrail/include/soc/irq.h>
+#include "../include/soc/baytrail.h"
 
 Scope(\)
 {

src/soc/intel/fsp_baytrail/bootblock/bootblock.c

@@ -19,12 +19,12 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/intel/microcode/microcode.c>
-#include <baytrail/iosf.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/spi.h>
-#include <baytrail/iomap.h>
-#include <baytrail/lpc.h>
-#include <baytrail/gpio.h>
+#include <soc/iosf.h>
+#include <soc/pci_devs.h>
+#include <soc/spi.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/gpio.h>
 #include <reset.h>
 
 /*

src/soc/intel/fsp_baytrail/chip.c

@@ -16,8 +16,8 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>
 #include "chip.h"
 

src/soc/intel/fsp_baytrail/cpu.c

@@ -27,11 +27,11 @@
 #include <cpu/x86/smm.h>
 #include <reg_script.h>
 
-#include <baytrail/msr.h>
-#include <baytrail/pattrs.h>
-#include <baytrail/ramstage.h>
+#include <soc/msr.h>
+#include <soc/pattrs.h>
+#include <soc/ramstage.h>
 #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
-#include <baytrail/smm.h>
+#include <soc/smm.h>
 
 static void smm_relocate(void *unused);
 static void enable_smis(void *unused);

src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c

@@ -21,18 +21,18 @@
 #include <cbmem.h>
 #include <device/device.h>
 #include <device/pci_def.h>
-#include <baytrail/pci_devs.h>
+#include <soc/pci_devs.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>
 #include "../chip.h"
 #include <arch/io.h>
-#include <baytrail/reset.h>
-#include <baytrail/pmc.h>
-#include <baytrail/acpi.h>
-#include <baytrail/iomap.h>
-#include <baytrail/smm.h>
+#include <soc/reset.h>
+#include <soc/pmc.h>
+#include <soc/acpi.h>
+#include <soc/iomap.h>
+#include <soc/smm.h>
 
 #ifdef __PRE_RAM__
-#include <baytrail/romstage.h>
+#include <soc/romstage.h>
 #endif
 
 #ifdef __PRE_RAM__

src/soc/intel/fsp_baytrail/gpio.c

@@ -15,9 +15,9 @@
 
 #include <device/pci.h>
 #include <console/console.h>
-#include <baytrail/gpio.h>
-#include <baytrail/pmc.h>
-#include <baytrail/smm.h>
+#include <soc/gpio.h>
+#include <soc/pmc.h>
+#include <soc/smm.h>
 
 /*
  * GPIO-to-Pad LUTs

src/soc/intel/fsp_baytrail/i2c.c

@@ -14,11 +14,11 @@
  */
 
 #include <device/pci.h>
-#include <baytrail/baytrail.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/iosf.h>
+#include <soc/baytrail.h>
+#include <soc/pci_devs.h>
+#include <soc/iosf.h>
 #include <delay.h>
-#include <baytrail/i2c.h>
+#include <soc/i2c.h>
 
 /* Wait for the transmit FIFO till there is at least one slot empty.
  * FIFO stall due to transmit abort will be checked and resolved

src/soc/intel/fsp_baytrail/include/soc/acpi.h

@@ -18,7 +18,7 @@
 #define _BAYTRAIL_ACPI_H_
 
 #include <arch/acpi.h>
-#include <baytrail/nvs.h>
+#include <soc/nvs.h>
 #include <device/device.h>
 
 void acpi_create_intel_hpet(acpi_hpet_t * hpet);

src/soc/intel/fsp_baytrail/include/soc/gpio.h

@@ -18,7 +18,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
-#include <baytrail/iomap.h>
+#include <soc/iomap.h>
 
 /* #define GPIO_DEBUG */
 

src/soc/intel/fsp_baytrail/include/soc/iosf.h

@@ -17,7 +17,7 @@
 #define _BAYTRAIL_IOSF_H_
 
 #include <stdint.h>
-#include <baytrail/pci_devs.h>
+#include <soc/pci_devs.h>
 
 /*
  * The Bay Trail SoC has a message network called IOSF Sideband. The access

src/soc/intel/fsp_baytrail/include/soc/nvs.h

@@ -17,7 +17,7 @@
 #ifndef _BAYTRAIL_NVS_H_
 #define _BAYTRAIL_NVS_H_
 
-#include <baytrail/device_nvs.h>
+#include <soc/device_nvs.h>
 
 typedef struct {
 	/* Miscellaneous */

src/soc/intel/fsp_baytrail/iosf.c

@@ -15,7 +15,7 @@
  */
 
 #include <arch/io.h>
-#include <baytrail/iosf.h>
+#include <soc/iosf.h>
 
 #if !defined(__PRE_RAM__)
 #define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12))

src/soc/intel/fsp_baytrail/memmap.c

@@ -16,8 +16,8 @@
 
 #include <arch/io.h>
 #include <cbmem.h>
-#include <baytrail/iosf.h>
-#include <baytrail/smm.h>
+#include <soc/iosf.h>
+#include <soc/smm.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>
 
 uintptr_t smm_region_start(void)

src/soc/intel/fsp_baytrail/northcluster.c

@@ -20,13 +20,13 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <cpu/x86/lapic.h>
-#include <baytrail/iomap.h>
-#include <baytrail/iosf.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
+#include <soc/iomap.h>
+#include <soc/iosf.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 #include <device/pci.h>
 #include <cbmem.h>
-#include <baytrail/baytrail.h>
+#include <soc/baytrail.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>
 #include <arch/acpi.h>
 

src/soc/intel/fsp_baytrail/nvm.c

@@ -20,7 +20,7 @@
 #include <string.h>
 #include <spi-generic.h>
 #include <spi_flash.h>
-#include <baytrail/nvm.h>
+#include <soc/nvm.h>
 
 /* This module assumes the flash is memory mapped just below 4GiB in the
  * address space for reading. Also this module assumes an area it erased

src/soc/intel/fsp_baytrail/placeholders.c

@@ -2,7 +2,7 @@
 #include <arch/acpi.h>
 #include <cpu/cpu.h>
 #include <device/pci_rom.h>
-#include <baytrail/acpi.h>
+#include <soc/acpi.h>
 
 
 void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {}

src/soc/intel/fsp_baytrail/pmutil.c

@@ -17,10 +17,10 @@
 #include <arch/io.h>
 #include <console/console.h>
 
-#include <baytrail/iomap.h>
-#include <baytrail/lpc.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
 
 #if defined(__SMM__)
 

src/soc/intel/fsp_baytrail/ramstage.c

@@ -26,13 +26,13 @@
 #include <stdlib.h>
 #include <string.h>
 
-#include <baytrail/gpio.h>
-#include <baytrail/lpc.h>
-#include <baytrail/nvs.h>
-#include <baytrail/msr.h>
-#include <baytrail/pattrs.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
+#include <soc/gpio.h>
+#include <soc/lpc.h>
+#include <soc/nvs.h>
+#include <soc/msr.h>
+#include <soc/pattrs.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 
 /* Global PATTRS */
 DEFINE_PATTRS;

src/soc/intel/fsp_baytrail/reset.c

@@ -14,8 +14,8 @@
  */
 
 #include <arch/io.h>
-#include <baytrail/pmc.h>
-#include <baytrail/reset.h>
+#include <soc/pmc.h>
+#include <soc/reset.h>
 
 void cold_reset(void)
 {

src/soc/intel/fsp_baytrail/romstage/pmc.c

@@ -18,12 +18,12 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci_def.h>
-#include <baytrail/iomap.h>
-#include <baytrail/iosf.h>
-#include <baytrail/lpc.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/romstage.h>
+#include <soc/iomap.h>
+#include <soc/iosf.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/romstage.h>
 #include "../chip.h"
 
 void tco_disable(void)

src/soc/intel/fsp_baytrail/romstage/report_platform.c

@@ -16,10 +16,10 @@
 
 #include <console/console.h>
 #include <arch/io.h>
-#include <baytrail/iosf.h>
-#include <baytrail/romstage.h>
+#include <soc/iosf.h>
+#include <soc/romstage.h>
 #include <cpu/x86/msr.h>
-#include <baytrail/msr.h>
+#include <soc/msr.h>
 #include <cpu/x86/name.h>
 
 static void print_dram_info(void)

src/soc/intel/fsp_baytrail/romstage/romstage.c

@@ -26,16 +26,16 @@
 #include <cpu/x86/mtrr.h>
 #include <romstage_handoff.h>
 #include <timestamp.h>
-#include <baytrail/gpio.h>
-#include <baytrail/iomap.h>
-#include <baytrail/lpc.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/romstage.h>
-#include <baytrail/acpi.h>
-#include <baytrail/baytrail.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+#include <soc/acpi.h>
+#include <soc/baytrail.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>
-#include <baytrail/pmc.h>
-#include <baytrail/spi.h>
+#include <soc/pmc.h>
+#include <soc/spi.h>
 #include <version.h>
 #include <pc80/mc146818rtc.h>
 #include <device/pci_def.h>

src/soc/intel/fsp_baytrail/romstage/uart.c

@@ -14,11 +14,11 @@
  */
 
 #include <arch/io.h>
-#include <baytrail/gpio.h>
-#include <baytrail/iomap.h>
-#include <baytrail/lpc.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/romstage.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
 
 void byt_config_com1_and_enable(void)
 {

src/soc/intel/fsp_baytrail/smihandler.c

@@ -23,9 +23,9 @@
 #include <elog.h>
 #include <halt.h>
 
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/nvs.h>
 
 /* GNVS needs to be set by coreboot initiating a software SMI. */
 static global_nvs_t *gnvs;

src/soc/intel/fsp_baytrail/smm.c

@@ -22,9 +22,9 @@
 #include <cpu/x86/smm.h>
 #include <string.h>
 
-#include <baytrail/iomap.h>
-#include <baytrail/pmc.h>
-#include <baytrail/smm.h>
+#include <soc/iomap.h>
+#include <soc/pmc.h>
+#include <soc/smm.h>
 
 /* Save the gpio route register. The settings are committed from
  * southcluster_smm_enable_smi(). */

src/soc/intel/fsp_baytrail/southcluster.c

@@ -30,15 +30,15 @@
 #include <pc80/i8259.h>
 #include <pc80/isa-dma.h>
 
-#include <baytrail/baytrail.h>
-#include <baytrail/iomap.h>
-#include <baytrail/irq.h>
-#include <baytrail/lpc.h>
-#include <baytrail/nvs.h>
-#include <baytrail/acpi.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/ramstage.h>
+#include <soc/baytrail.h>
+#include <soc/iomap.h>
+#include <soc/irq.h>
+#include <soc/lpc.h>
+#include <soc/nvs.h>
+#include <soc/acpi.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/ramstage.h>
 #include "chip.h"
 #include <arch/acpi.h>
 #include <arch/acpigen.h>

src/soc/intel/fsp_baytrail/spi.c

@@ -23,8 +23,8 @@
 #include <device/pci_ids.h>
 #include <spi_flash.h>
 
-#include <baytrail/lpc.h>
-#include <baytrail/pci_devs.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
 
 #ifdef __SMM__
 #define pci_read_config_byte(dev, reg, targ)\

src/soc/intel/fsp_baytrail/tsc_freq.c

@@ -16,7 +16,7 @@
 #include <stdint.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/tsc.h>
-#include <baytrail/msr.h>
+#include <soc/msr.h>
 
 unsigned bus_freq_khz(void)
 {
@@ -49,9 +49,9 @@ unsigned long tsc_freq_mhz(void)
 
 #if !defined(__SMM__)
 #if !defined(__PRE_RAM__)
-#include <baytrail/ramstage.h>
+#include <soc/ramstage.h>
 #else
-#include <baytrail/romstage.h>
+#include <soc/romstage.h>
 #endif
 
 void set_max_freq(void)