Naresh G Solanki fb7937918a soc/intel/skylake: Enable XHCI clock gate control in ACPI ... Enable SS link trunk clock gating & D3hot when device enters D3 state. Similarly disable SS link trunk clock gating & D3hot when device enters D0 state TEST=Build & boot Poppy board. Check working for XHCI wake when DUT is in S3. Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/18879 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2017-04-07 21:44:29 +02:00
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broadcom/cygnus	vboot: Move remaining features out of vendorcode/google/chromeos	2017-03-28 22:18:13 +02:00
dmp/vortex86ex	src/soc: Capitalize CPU, ACPI, RAM and ROM	2016-07-31 19:27:53 +02:00
imgtec/pistachio	spi: Get rid of SPI_ATOMIC_SEQUENCING	2016-12-23 04:54:55 +01:00
intel	soc/intel/skylake: Enable XHCI clock gate control in ACPI	2017-04-07 21:44:29 +02:00
lowrisc/lowrisc	soc/lowrisc: Place CBMEM at top of autodetected RAM	2016-12-06 18:51:13 +01:00
marvell	vboot: Move remaining features out of vendorcode/google/chromeos	2017-03-28 22:18:13 +02:00
mediatek/mt8173	vboot: Move remaining features out of vendorcode/google/chromeos	2017-03-28 22:18:13 +02:00
nvidia	vboot: Move remaining features out of vendorcode/google/chromeos	2017-03-28 22:18:13 +02:00
qualcomm	Remove libverstage as separate library and source file class	2017-03-28 22:18:53 +02:00
rdc/r8610	rdc/r8610: Move to src/soc	2016-05-05 20:08:58 +02:00
rockchip	Remove libverstage as separate library and source file class	2017-03-28 22:18:53 +02:00
samsung	vboot: Select SoC-specific configuration for all Chrome OS boards	2017-03-28 22:12:54 +02:00
ucb/riscv	soc/ucb/riscv: Place CBMEM at top of autodetected RAM	2016-12-06 18:48:28 +01:00