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Shreesh Chhabbi fbad99f347 soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
This change uses the following information to determine the
appropriate S0ix states to enable as per PDG document: 607872
for TGL UP3 UP Rev2p2 (section 10.13):

1. SoC - UP3 v/s UP4
2. H/W design - external phy gating, external clk gating, external bypass
3. Devices enabled at runtime - CNVi, ISH

In some cases, it is recommended to use a shallower state for
S0ix even if the higher state can be achieved (e.g. with external
gating not enabled). This recommendation is because the shallower
state is determined to provide better power savings as per the
above document. Deepest state expected on tigerlake up3 based
platforms is S0i3.2.

BUG=b:177821896
TEST=Build coreboot for volteer. Verify that deepest
S0ix substate that is enabled is S0i3.1

Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49766
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 07:23:09 +00:00
3rdparty Update chromeec submodule to upstream master 2021-02-06 10:47:13 +00:00
Documentation Doc/mb/lenovo/montevina_series: Use Makefile to generate IFD 2021-02-09 07:48:13 +00:00
LICENSES
configs mb/system76/oryp5: Add System76 Oryx Pro 5 2021-01-28 09:15:00 +00:00
payloads tint: update the archive from 0.04+nmu1 to 0.05 2021-02-07 22:00:23 +00:00
src soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design 2021-02-10 07:23:09 +00:00
tests tests: Add lib/region_file-test test case 2021-02-02 18:05:26 +00:00
util util/bincfg: Add MAC address example to gbe-ich9m.set 2021-02-09 07:49:22 +00:00
.checkpatch.conf
.clang-format
.editorconfig
.gitignore .gitignore: Ignore .test/.dependencies globally 2020-10-31 18:21:36 +00:00
.gitmodules 3rdparty: Add STM as a submodule 2020-09-30 10:17:03 +00:00
.gitreview
AUTHORS
COPYING
MAINTAINERS MAINTAINERS: Add myself to MAINTAINERS 2021-01-26 22:22:21 +00:00
Makefile Makefile: Add $(xcompile) to specify where to write xcompile 2020-12-23 03:40:35 +00:00
Makefile.inc Makefile.inc: Avoid --emit-relocs on RISC-V 2021-01-22 02:13:11 +00:00
README.md
gnat.adc
toolchain.inc

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.