coreboot-kgpe-d16/src
Kyösti Mälkki bf62b2ddb0 AMD fam10: Drop PCI_BUS_SEGN_BITS
All boards in tree use 0.  Looks like this is all work that was
never completed and tested.

We also have static setting sysconf.segbit=0 which would conflict
with PCI_BUS_SEGN_BITS>0.

Having PCI_BUS_SEGN_BITS>0 would also require PCI MMCONF support
to cover over 255 buses.

Change-Id: I060efc44d1560541473b01690c2e8192863c1eb5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8554
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-09 19:33:08 +01:00
..
arch AMD fam10: Drop PCI_BUS_SEGN_BITS 2015-03-09 19:33:08 +01:00
console Add stage information to coreboot banner 2015-03-04 19:46:25 +01:00
cpu cpu/Kconfig: Make in-tree microcode generation dependent on BLOBs repository 2015-03-09 03:35:33 +01:00
device AMD fam10: Drop PCI_BUS_SEGN_BITS 2015-03-09 19:33:08 +01:00
drivers drivers/i2c/w83793: Use devicetree.cb to set additional values 2015-02-26 06:20:07 +01:00
ec acpi: Generate valid ACPI processor objects 2015-02-16 21:02:30 +01:00
include build.h: remove variable for the builduser, -hostname and -domain 2015-03-09 17:53:16 +01:00
lib build.h: remove variable for the builduser, -hostname and -domain 2015-03-09 17:53:16 +01:00
mainboard AMD fam10: Always have AMDMCT 2015-03-09 06:00:07 +01:00
northbridge AMD fam10: Drop PCI_BUS_SEGN_BITS 2015-03-09 19:33:08 +01:00
soc broadwell: enable PCIe endpoint CLK power management 2015-03-09 03:33:52 +01:00
southbridge x86: Fix pointer arithmetic regressions from MMIO changes 2015-02-27 18:15:33 +01:00
superio superio/fintek/f81216h: Add the correct unlock key values 2015-02-14 00:53:26 +01:00
vendorcode AMD: Uniformly define MSRs for TOP_MEM and TOP_MEM2 2015-03-07 21:22:20 +01:00
Kconfig nvram: Add option to reset NVRAM to default parameters on every boot 2015-02-16 08:36:37 +01:00