Marshall Dawson fdff6c25a1 soc/amd/stoneyridge: Remove errant parenthesis in southbridge.h ... Delete an unmatched opening parenthesis in the definition for the EHCI hub config register definition. This wasn't causing a problem unless EHCI debug was enabled. TEST=Jam Makefile.inc to unconditionally build enable_usbdebug.c and verify successful build Change-Id: I5f461d1573e416b5a8ee24329142e3c46b6a05e3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29073 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2018-10-14 19:11:41 +00:00
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amd	soc/amd/stoneyridge: Remove errant parenthesis in southbridge.h	2018-10-14 19:11:41 +00:00
broadcom	soc/broadcom/cygnus: Increase romstage SRAM size in memlayout	2018-08-13 12:16:32 +00:00
cavium	soc/cavium: dynamic UART initialization for cavium cn8100	2018-10-10 16:37:38 +00:00
imgtec	src: Use tabs for indentation	2018-10-08 09:46:16 +00:00
intel	drivers/intel/fsp2_0: Hook up IntelFSP repo	2018-10-12 23:20:53 +00:00
lowrisc/lowrisc	mb/lowrisc: Remove the Nexys4DDR port	2018-09-26 15:36:40 +00:00
mediatek	mediatek/mt8183: Init PLLs for DRAM	2018-10-10 12:16:43 +00:00
nvidia	tegra124_lp0: make sure to build with compiler.h included	2018-10-11 11:00:49 +00:00
qualcomm	Move compiler.h to commonlib	2018-10-08 16:57:27 +00:00
rockchip	drivers/i2c: Add i2c TPM support for different stages	2018-08-10 23:25:52 +00:00
samsung	Move compiler.h to commonlib	2018-10-08 16:57:27 +00:00
sifive	soc/sifive/fu540: Document #if ENV_ROMSTAGE line	2018-09-26 18:52:54 +00:00
ucb	arch/riscv: provide a monotonic timer	2018-09-14 09:28:06 +00:00