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coreboot-kgpe-d16/src/soc/intel
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Duncan Laurie fe85ae3f41 skylake: PCR: Add Port ID for SCS 
Add the PCR Port ID for the storage controllers and
reformat to put the PCR PIDs in increasing order.

BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: I0f0144ef79d3691fa120dafc9a31d2a681bf2a28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 208242f58759899f17e52593ed6e1dd631334ac9
Original-Change-Id: I942bcf01b0576136c0039aa62f38fe7f3454ba8a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295905
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11532
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08 11:17:15 +00:00
..
baytrail Drop "See file CREDITS..." comment 2015-09-07 15:54:50 +00:00
braswell microcode: Unify rules to add microcode to CBFS once again 2015-09-07 23:51:30 +00:00
broadwell Drop "See file CREDITS..." comment 2015-09-07 15:54:50 +00:00
common bootstate: remove need for #ifdef ENV_RAMSTAGE 2015-09-04 21:01:58 +00:00
fsp_baytrail intel/fsp_baytrail: Support Baytrail FSP Gold4 release 2015-07-21 22:32:23 +02:00
skylake skylake: PCR: Add Port ID for SCS 2015-09-08 11:17:15 +00:00