Add the PCR Port ID for the storage controllers and
reformat to put the PCR PIDs in increasing order.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I0f0144ef79d3691fa120dafc9a31d2a681bf2a28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 208242f58759899f17e52593ed6e1dd631334ac9
Original-Change-Id: I942bcf01b0576136c0039aa62f38fe7f3454ba8a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295905
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11532
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There are a few places in ACPI that touch PCR registers,
either to read a value or to set some magic bits.
Expose some functions for this that will keep all the PCR
access in one location instead of spread throughout the code.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: Iafeb3e2cd8f38af10d29eaaf18f2380c5651fe6d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e78b2801fbc5c00ba452ae5e4ecb07c3e23bf6c1
Original-Change-Id: I2e4d491157f7ac6d2ebc231b11661c059b4a7fa0
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295904
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11531
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Clean up the code in pch.asl:
- move all the C header includes into here instead of duplicated
in various ASL files included from here
- move the trap field definition into platform.asl with the method
- alphebetize the includes
- move gpio.asl include into pch.asl
- remove duplicate irqlinks.asl include from lpc.asl
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I51b1c5286fc344df6942a24c1dea71abf10ab561
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3ee9c4afa031191d275f0d3d40b2b15b85369b2f
Original-Change-Id: I3bae434ad227273885d8436db23e17e593739f77
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295903
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11530
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the code for PCIE _PRT entries to use an actual root
port number from the device instead of NVS that was never
initialized from zero.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=build and boot on glados with pci=nomsi to ensure interrupts work
Change-Id: I76ff07d2bf7001aed504558d55cca9e19c692d7e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d43392199ec5f37150f2b13732924c47b8dc830c
Original-Change-Id: I1132f1dc47122db08d1b798a259ee9b52a488f5e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295902
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11529
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that cbfstool supports file alignment, we can use the conveniently
available <filename>-align handler, and remove the need to have a
separate rule in src/Makefile.inc just for adding the microcode.
We can also get rid of the layering violation of having the
CONFIG_PLATFORM_USES_FSP1_0 symbol in a generic src/cpu/ makefile.
Note that we still have a layering violation by the use of the
CONFIG_CPU_MICROCODE_CBFS_LOC symbol, but this one is acceptable
for the time being.
Change-Id: Id2f8c15d250a0c75300d0a870284cac0c68a311b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11526
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
coreboot has no CREDITS file.
Change-Id: Iaa4686979ba1385b00ad1dbb6ea91e58f5014384
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11514
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The BOOT_STATE_INIT_ENTRY macro can only be used in ramstage, however
the current state of the header meant bad build errors in non-ramstage.
Therefore, people had to #ifdef in the source. Remove that requirement.
Change-Id: I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11492
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
When building up which files to include in romstage there
were both 'cpu_incs' and 'cpu_incs-y' which were used to
generate crt0.S. Remove the former to settle on cpu_incs-y
as the way to be included.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built rambi. No include file changes.
Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11494
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This depends on RELOCATABLE_RAMSTAGE, and shouldn't be selected if
its dependency is not activated.
Change-Id: I8e7efc3f87e105715fe3377ed306891f0d209979
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11473
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This option was removed in the following commit:
* 80f5d5b fsp1_1: remove duplicate mrc caching mechanism
Change-Id: I08ef4fc6029cc066e4f7b9c82b6b187a9794afdb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11462
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is just wrong. PAYLOAD_SEABIOS tells us nothing about whether
or not the payload will actually be SeaBIOS:
1. PAYLOAD_SEABIOS, but payload changed with cbfstool
2. !PAYLOAD_SEABIOS, but an elf payload was added which is SeaBIOS
et. cetera.
Change-Id: I4c17e8dde20bf21537f542fda2dad7d3a1894862
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11293
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
This patch adds the ASL files with the DPTF related settings and the
thermal devices enabled in the SOC. It also enables the DPTF setting
at the global NVS level.
BRANCH=None
BUG=chrome-os-partner:40855
TEST=Built for kunimitsu board. Tested to see that the thermal devices
and the participants are enumerated and can be seen in the
/sys/bus/platform/devices. Also checked the temperature readings of the
cooling devices and the thermal zones enumerated in the /sys/class/thermal.
Change-Id: I8ad044eaf1ad488fb1682097da83b40d2bede414
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 7624eeca19b4f286b30c3d4ac5b44c5e9619c2c7
Original-Change-Id: I0d92ef42cff5567ea6fc566730588802d8549ce0
Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/293391
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Reviewed-on: http://review.coreboot.org/11430
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Early(romstage) SPI write protected status read(wpsr) functionality
was broken causing 2 sec timeout issue.Implementing HW Seq based rd
status operation in romstage.
BRANCH=NONE
BUG=chrome-os-partner:42115
TEST=Built for sklrvp and kunimitsu and tested using below command
flashrom -p host --wp-enable [this should enable WP on flash chip]
Read using romstage SPI.c. WPSR=0x80 (CB is reading Bit 7 as locked)
flashrom -p host --wp-disable [this should disable WP on flash chip]
Read using romstage SPI.c. WPSR=0x00 (CB is reading Bit 7 as unlocked)
Change-Id: I79f6767d88f766be1b47adaf7c6e2fa368750d5a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 4b798c44634581ebf7cdeea76c486e95e1f0a488
Original-Change-Id: I7e9b02e313b84765ddfef06724e9921550c4e677
Original-Signed-off-by: Subrata <subrata.banik@intel.com>
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/294445
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11423
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The RMT flag that was attempting to disable saved training to
force a full memory train was happening too late. In testing
I was actually hitting a case where FSP was training every time
but it was not because it was properly being told to.
This moves the check of the RMT flag from devicetree to happen
ealier, before it is actually consumed by romstage_common().
BUG=chrome-os-partner:40635
BRANCH=none
TEST=do both power off+on and warm resets to ensure that FSP
is doing a full memory train every time with RMT enabled.
Change-Id: Icf36e7b1ae20e08f6bc24bf832498d69b37dee92
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: f3fa3846d51dec65f22f018acc8fb8c4d18688a7
Original-Change-Id: I2128b4a24bb8b2c8ddcb792c09b6fb0284d1fda4
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294177
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11417
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The previously driven TX state of the buffer was not
being cleared before or'ing in the new value. Fix this
oversight.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados. Also dumped assembly and saw the
masking happen.
Change-Id: I74ea469564d37d6b29e9481b0ea704f04f54ac30
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: d399e8b32b30b8b2275bb6ff8dd24f7d5cfeadda
Original-Change-Id: I341b396af5de20ffeeb2e42066b224dd54251793
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294541
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11416
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
RMT is useless if the memory does not do a full training pass,
and since FSP does not seem to handle that case itself have
coreboot not pass in a valid set of saved training data so FSP
will do a full memory train.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot twice on glados with p2 and RMT enabled
and see it do a full memory train on each boot.
Change-Id: Ia4f29a937e726a5a676f056ce8970086988da5b6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: f01e99204409899d4adbaebbe221b0348975cfa6
Original-Change-Id: I0bb193c5f3c9206a67315906745aad96a95b3f74
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294067
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11414
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The SOC handler for memory init params is only taking UPD
as an input which does not allow it to use romstage_params.
In addition the UPD input is called params which is confusing
so rename it to upd so romstage_params can be passed properly.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados p2
Change-Id: I414610fee2b5d03a8e2cebfa548ea8bf49932a48
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: db94d6f3e6cad721de2188a136df10ccf66aff6a
Original-Change-Id: I7ec15edd4a16df121c5967aadd8b2651267ec773
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294066
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11413
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The BUNIT controls the policy for read/write access to physical
memory. For the SMRAM range the policy was not allowing dirty
evictions to the SMRAM when the core causing the eviction was not
in SMM mode. This could happen when the SMM handler dirtied a line
and then RSM'd back into non-SMM mode. The cache line was dirtied
while in SMM mode, but when that particular cache line was evicted
it would be silently dropped. Fix this by allowing the BUNIT to honor
writes to the SMRAM range while the evicting core is not in SMM mode.
The core SMRR msr provides the mechanism for disallowing general access
to the SMRAM region while it is not in SMM mode.
BUG=chrome-os-partner:43091
BRANCH=None
TEST=Run suspend_stress_test and ensure there is no hang SMI handler
on suspend-path.
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Change-Id: Ie794aa3afd54b5e21d0d59a2a7388d507f233537
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 9c481ab339b4e5ab063e2c32b1f0a48b521142b2
Original-Change-Id: I3e7d41c794c6168eb2ad4eb047675bdb1728f72f
Original-Reviewed-on: https://chromium-review.googlesource.com/292890
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: http://review.coreboot.org/11412
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CBFS_SIZE is living as a mainboard attribute. Because
of the Kconfig include ordering the SoC *cannot* set
the default.
BUG=chrome-os-partner:43419
BRANCH=None
TEST=None
Change-Id: If34e8fd965573fdc7f57b63201dbcb5256e132d6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: a820b11a0aa3b820c79b1f76b15370d969153175
Original-Change-Id: I7ba637e66878f5ae9caedb63fdd37ed7e375224e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289832
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11410
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It doesn't make sense to die() when printing information. In fact the
die() are protected by DISPLAY_HOBS config option. This can get
confusing, so replace die() calls with printk().
Also since these messages are designed to be informational, keep them
at BIOS_INFO log level.
Change-Id: Id75b9a54f4aea23074a7489d12809cc2da05f1cd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11456
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The code in mrc_cache.c doesn't check for the presence of 'mrc.cache',
and just returns hardcoded value for he location of he MRC cache. This
becomes a problem when there is a CBFS file at the same location,
which can get overwritten. A CBFS file is created to cover this region
so that nothing can be added there.
This has the advantage of creating a build time error if another cbfs
file is hardcoded over the same region.
The default location of the MRC cache is also moved to 4G - 128K to
ensure that it defaults to something within CBFS.
Change-Id: Ic029c182f5a2180cb680e09b25165ee303a448a3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11440
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Aaron Durbin found that soc/common is already included as a subdir via
the wildcard in Makefile.inc:
subdirs-y += $(wildcard src/soc/*/*)
Since the entire file is protected by CONFIG_SOC_INTEL_COMMON, there
is no problem with including it for every platform. On the other hand,
when it is included by the skylake and braswell makefiles, any rule is
duplicated. As a result fix the braswell and skylake makefiles.
Change-Id: If5bad903c78dbce418852935ee55cdc7162b3b2d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11439
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The acpi_fill_ssdt_generator function pointer is evaluated for
each device. As there are multiple cpus in the system the
acpi_fill_ssdt_generator was being called more than once creating
duplicate ACPI entries because there was more than 1 cpu device.
Fix this by only generating them once by removing the
acpi_fill_ssdt_generator for the cpu devices, but add the
generator to the cpu cluster device.
BUG=chrome-os-partner:44084
BRANCH=None
TEST=Built and booted on glados. Noted ACPI entries only generated once.
Original-Change-Id: I695c30e6150f6d3a79d13744c532f1b658b10402
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294240
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Change-Id: I7c85f44ba65398bda668e13db8be531535a983c5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11285
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The prior implementation of PAD_CFG_GPI kept the pad
ownership as ACPI. The gpio driver in the kernel then
wouldn't allow one to export those GPIOs through sysfs
in /sys/class/gpio. Fix this by setting the ownership
to GPIO.
BUG=chrome-os-partner:44147
BRANCH=None
TEST=Built and boot glados. PCH_WP gpio is properly exported
by crossystem.
Original-Change-Id: I9fc7ab141a3fd74e0ff8b3ff5009b007b8a0d69b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294081
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ifbb61c5d64bb6a04f140685c70f4681e2babecef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11283
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The Kconfig symbol CACHE_MRC_BIN was getting forced enabled everywhere
it existed.
Remove the Kconfig symbol and get rid of the #if statements
surrounding the code.
This fixes the Kconfig warning for Haswell & Broadwell chips:
warning: (NORTHBRIDGE_INTEL_HASWELL &&
NORTHBRIDGE_INTEL_SANDYBRIDGE &&
NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE &&
NORTHBRIDGE_INTEL_IVYBRIDGE &&
NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE &&
CPU_SPECIFIC_OPTIONS) selects CACHE_MRC_BIN
which has unmet direct dependencies
(CPU_INTEL_SOCKET_RPGA988B || CPU_INTEL_SOCKET_RPGA989)
Change-Id: Ie0f0726e3d6f217e2cb3be73034405081ce0735a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11270
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
cbmem_top was using CHIPSET_RESERVED_MEM_BYTES to w/a unknown memory
regions reserved by fsp for chipset use. With that being removed, the
function needs to properly walk though the memory map resulted from fsp
memory init to find out the usable address for cbmem root.
Refer the FSP 1.3.0 Integartion guide for more details on the Memory
Map.
systemagent should also use the same mechanism to create the reserved
RAM resource.
BRANCH=None
BUG=None
TEST=Build and Boot kunimitsu (FAB3)
CQ-DEPEND=CL:*226035,CL:*226045,CL:291573
Original-Change-Id: Id0954cf8e6388e549c7d4df67b468572b5bea539
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291611
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Robbie Zhang <robbie.zhang@intel.com>
Change-Id: I4e716170f40936081ce9d4878bf74c75f469f78d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: http://review.coreboot.org/11239
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The skylake IO-APIC supports up to 120 redirection entries.
In practice it seems FSP has already written to this write-once
register. However, it doesn't hurt to actually be correct within
the source.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I666b1b6034f0d37a37ea918f802317f9d5f15718
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293251
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I6ddbc89c98c262e2dd0f9f0b76adb092d3043602
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11235
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
One thing that is brittle is lining up GPE0 bits in ASL
and with a board's design proper. This results in open
calculated magic numbers. To help alleviate this provide
just #defines that C preprocessor can use before handing
the source off to the ASL compiler.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados. Everything's intact.
Original-Change-Id: I359616ebe4bfc83c05bafe0ca36b766efd16dcca
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293410
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I32513c324b923fa0adbd6a0ee920c27e9b97dd1b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11233
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Broadwell and Skylake chipsets, along with a few mainboards were
selecting ALWAYS_LOAD_OPROM without making sure that the dependency
for that symbol was met as well.
Looking at the dependencies for VGA_RUN_ROM, we see:
PCI && !PAYLOAD_SEABIOS && !MAINBOARD_DO_NATIVE_VGA_INIT
Since ARCH_X86 selects PCI, that's always met here.
Since Broadwell and Skylake don't have native VGA init yet, that's
not needed.
- Make sure that VGA_RUN_ROM is selected as well.
- Add dependency on !PAYLOAD_SEABIOS for both ALWAYS_LOAD_OPROM and
VGA_RUN_ROM symbols where they're selected.
Fixes Kconfig warning for these boards and chipsets:
warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS &&
BOARD_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS)
selects ALWAYS_LOAD_OPROM which has unmet direct dependencies
(VGA_ROM_RUN)
Change-Id: I787a87e9467e1fc7afe8b04864b2a89b54824b9f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11246
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change the dependency on CONSOLE_SERIAL to select CONSOLE_SERIAL based
on this question.
The dependency was causing multiple warnings on every platform tested.
src/console/Kconfig:21:error: recursive dependency detected!
src/console/Kconfig:21: symbol CONSOLE_SERIAL depends on
DRIVERS_UART_8250MEM
src/drivers/uart/Kconfig:16: symbol DRIVERS_UART_8250MEM is selected by
UART_DEBUG
src/soc/intel/skylake/Kconfig:198: symbol UART_DEBUG depends on
CONSOLE_SERIAL
Change-Id: Ia0426cd150561694081b5ea7c6797d36022c1f57
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11243
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The current construction for processing SMI GPI events
didn't allow for the mainboard to query the state of a
particular GPI for the snapshotted SMI event. The
skylake part can route GPIs from any (there are design
limitations) GPIO group. Those status and enable registers
are within the GPIO community so one needs to gather
all the possibilities in order to query the state.
The call chain did this:
southbridge_smi_gpi(
clear_alt_smi_status() -> reset_alt_smi_status() ->
print_all_smi_status() -> return 0)
As a replacement the following functions and types are
introduced:
struct gpi_status - represent gpi status.
gpi_status_get() - per gpi query on struct gpi_status
gpi_clear_get_smi_status() - clear and retrieve SMI GPI status
mainboard_smi_gpi_handler() - mainboard handler using gpi_status
Also remove gpio_enable_all_smi() as that construct was never
used, but it also is quite heavy handed in that it would
enable SMI generation for all GPIs.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built.
Original-Change-Id: Ief977e60de65d9964b8ee58f2433cae5c93872ca
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291933
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ida009393c6af88ffe910195dc79a4c0d2a4c029e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11208
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The first pass of the GPIO configuration patch didn't
enable the SMI# generation for GPIs marked as SMI
routed. Now when a pad is configured as SMI routed
the bit for the SMI enablement is set accordingly.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built and booted glados. Confirmed SMI_EN being set
for SMI routed GPIOs.
Original-Change-Id: I796b68accb7a49b03ef18539861e72fa9d169c26
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/292010
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I3be770234d3f605ae630ecd5cd4cfe4867243999
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11207
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The gpio pad configuration currently defaults to ACPI
owned GPIs. A '0' was used which wasn't so clear. Add
a comment and explicitly set it to ACPI. Also,
PAD_CFG_GPI_ACPI_SMI wasn't using the _PAD_CFG_ATTRS
macro which causes compliation errors if attempted
to be instantiated. No piece of code tried to use
it so the error was overlooked.
Lastly, allow for soc/gpio.h to be included during
ASL compilation. That allows for gpio_defs.h to be
included and those macros utilized without needing
to know the file name and where it lives; just use
the generic gpio.h.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I9dbadb0b494683ab38babfc1ac5e13093ee37730
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291935
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id4fa8b65ec1e1537dbf09824c2155119a768807e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11206
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Instead of using a hard-coded value leverage the existing
definitions to perform GPE0 block length calculations. There
are 4 pairs of 32-bit status/enable registers.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I14d08298b5750c91ce0ac3fa33569813396f7089
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291932
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I127f026f15180fa79625d4cad96d5e35f85e5090
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11205
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The ec_smi_gpio and alt_gp_smi_en devicetree options are
goign to be removed. The plan for skylake is to set the
settings by the mainboard through either gpio pad
configuration or through helper functions.
Moreover, these values only allow *1* SMI GPIO configuration
in that the following has to be true:
alt_gp_smi_en = 1 << (ec_smi_gpio % 24)
If not, then another gpio(s) from the same group has the
SMI_EN bit set for it.
Lastly, remove all the subsequent dependencies as they are
no longer used: enable_alt_smi() and gpio_enable_group().
BUG=chrome-os-partner:43778
BRANCH=None
TEST=None
Original-Change-Id: I749a499c810d83de522a2ccce1dd9efb0ad2e20a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291931
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I2e1cd6879b76923157268a1449c617ef2aada9c4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
On skylake the GPE0 routing can be dynamically changed to
a particular GPIO group. Provide the ability for the mainboard
to set the route accordingly. If any of the values in the
devicetree are the same the current setting in the PMC register
is used. The GPIO communities need to have matching configuration
for the plumbing to work properly.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built and booted glados w/ and w/o devicetree changes. Fields
are set accordingly.
Original-Change-Id: I263d648c8ea8a70b21570f01b333d05a5fa2a4e3
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291930
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I966d38bc197dbb52a2ba50927c06e243e169afbe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11203
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
IedSize is not used in replace of IED_REGION_SIZE.
Drop it from chip.h.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=Built, booted, suspended, resumed on glados.
Original-Change-Id: I38f6518701306c0ffc6d2b2e3fe01624a5eadf54
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290933
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Trybot-Ready: David James <davidjames@chromium.org>
Change-Id: I9dd9e689d4d4f7b4770369dcd042d3325990ae32
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11201
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The stage_cache_external_region() calculation is actually
dependennt on the properties of the chipset. The reason
is that certain regions within the SMRAM are used for
chipset-specific features. Therefore, provide an API
for abstracting the querying of subregions within
the SMRAM.
The 3 subregions introduced are:
SMM_SUBREGION_HANDLER - SMM handler area
SMM_SUBREGION_CACHE - SMM cache region
SMM_SUBREGION_CHIPSET - Chipset specific area.
The subregions can be queried using the newly
added smm_subregion() function.
Now stage_cache_external_region() uses smm_subregion()
to query the external stage cache in SMRAM, and this
patch also eliminates 2 separate implementations of
stage_cache_external_region() between romstage and
ramstage.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=Built, booted, suspended, resumed on glados.
Original-Change-Id: Id669326ba9647117193aa604038b38b364ff0f82
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290833
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Idb1a75d93c9b87053a7dedb82e85afc7df6334e0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11197
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The smm_subregion() support allows the SMM relocation
to not use duplicated math by calling out the specific
regions it wants. IED base is now correct and not
pointing outside from SMRAM.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=Built, booted, suspended, resumed on glados.
Original-Change-Id: Ief8940c2ab6320449500ced2121d0cd7ed73af4b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290930
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Trybot-Ready: David James <davidjames@chromium.org>
Change-Id: I00c3284cfacb2a73942640ccfa7912b7d65efb9d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11198
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The fsp_ramstage.c code was not taking advantage of the stage
cache which does all the accounting and calculation work for
the caller. Remove the open coded logic and use the provided
infrastructure. Using said infrastructure means there's no
need for the FSP_CACHE_SIZE Kconfig variable. Therefore, remove
it.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=Built, booted, suspended, and resumed on glados.
Original-Change-Id: I4363823c825b4a700205769f109ff9cf0d78b897
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290831
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ifd3cc4a538daac687949c5f4cab2c687368d6787
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11196
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The TSEG is defined to be from TSEG->BGSM in the
host bridge registers. Use those registers at
runtime to calculate the correct TSEG size.
Lastly, use a few helper macros to make constants
more readable.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built, booted, suspended, resumed on glados.
Original-Change-Id: I6db424a0057ecfc040a3cd5d99476c2fb8f5d29b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290832
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I6890fa450ce8dc10080321aa1a7580e0adc48ad5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11195
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Using struct prog and struct region_device allows for the
caller to be none-the-wiser about where FSP gets placed. It
also allows for the source location to be abstracted away
such that it doesn't require a large mapping up front to
do the relocation. Lastly, it allows for simplifying the
intel/commmon FSP support in that it can pass around a
struct prog.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=Built, booted, suspended, and resumed on glados.
Original-Change-Id: I034b04ab2b7e9e01f5ee14fcc190f04b90517d30
Original-Signed-off-by: Aaron Durbin <adurbin@chroumium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290830
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ibe1f206a9541902103551afaf212418fcc90e73c
Signed-off-by: Aaron Durbin <adurbin@chroumium.org>
Reviewed-on: http://review.coreboot.org/11193
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
