e1dad0c0b9
If a port is connected before and after an xhci controller reset, the PORTSC CSC bit may not be asserted. Add an additional check in xhci_rh_port_status_changed for the PRC bit so we can correctly handle ports in such a state. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I2d623aae647ab13711badd7211ab467afdc69548 Reviewed-on: https://chromium-review.googlesource.com/189394 Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit ee7c3ea182b35bb6ce3c62f301c4515714f6e654) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7002 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> |
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| .. | ||
| storage | ||
| usb | ||
| video | ||
| Makefile.inc | ||
| cbmem_console.c | ||
| hid.c | ||
| keyboard.c | ||
| nvram.c | ||
| options.c | ||
| pci.c | ||
| serial.c | ||
| speaker.c | ||