9418476524
This patch is a manual cleanup of all the rubble left by coccinelle waltzing through our code base. It's generally not very good with line breaks and sometimes even eats comments, so this patch is my best attempt at putting it all back together. Also finally remove those hated writel()-style macros from the headers. BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: Id572f69c420c35577701feb154faa5aaf79cd13e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 817402a80ab77083728b55aed74b3b4202ba7f1d Original-Change-Id: I3b0dcd6fe09fc4e3b83ee491625d6dced98e3047 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254865 Reviewed-on: http://review.coreboot.org/9837 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
147 lines
3.9 KiB
C
147 lines
3.9 KiB
C
/*
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* Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved.
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*/
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#include <delay.h>
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#include <soc/clock.h>
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#include <types.h>
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/**
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* uart_pll_vote_clk_enable - enables PLL8
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*/
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void uart_pll_vote_clk_enable(unsigned int clk_dummy)
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{
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setbits_le32(BB_PLL_ENA_SC0_REG, BIT(8));
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if (!clk_dummy)
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while((read32(PLL_LOCK_DET_STATUS_REG) & BIT(8)) == 0);
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}
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/**
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* uart_set_rate_mnd - configures divider M and D values
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*
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* Sets the M, D parameters of the divider to generate the GSBI UART
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* apps clock.
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*/
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static void uart_set_rate_mnd(unsigned int gsbi_port, unsigned int m,
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unsigned int n)
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{
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/* Assert MND reset. */
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setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7));
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/* Program M and D values. */
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write32(GSBIn_UART_APPS_MD_REG(gsbi_port), MD16(m, n));
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/* Deassert MND reset. */
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clrbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7));
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}
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/**
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* uart_branch_clk_enable_reg - enables branch clock
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*
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* Enables branch clock for GSBI UART port.
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*/
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static void uart_branch_clk_enable_reg(unsigned int gsbi_port)
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{
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setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(9));
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}
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/**
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* uart_local_clock_enable - configures N value and enables root clocks
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*
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* Sets the N parameter of the divider and enables root clock and
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* branch clocks for GSBI UART port.
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*/
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static void uart_local_clock_enable(unsigned int gsbi_port, unsigned int n,
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unsigned int m)
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{
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unsigned int reg_val, uart_ns_val;
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void *const reg = (void *)GSBIn_UART_APPS_NS_REG(gsbi_port);
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/*
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* Program the NS register, if applicable. NS registers are not
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* set in the set_rate path because power can be saved by deferring
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* the selection of a clocked source until the clock is enabled.
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*/
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reg_val = read32(reg); // REG(0x29D4+(0x20*((n)-1)))
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reg_val &= ~(Uart_clk_ns_mask);
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uart_ns_val = NS(BIT_POS_31,BIT_POS_16,n,m, 5, 4, 3, 1, 2, 0,3);
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reg_val |= (uart_ns_val & Uart_clk_ns_mask);
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write32(reg, reg_val);
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/* enable MNCNTR_EN */
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reg_val = read32(reg);
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reg_val |= BIT(8);
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write32(reg, reg_val);
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/* set source to PLL8 running @384MHz */
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reg_val = read32(reg);
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reg_val |= 0x3;
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write32(reg, reg_val);
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/* Enable root. */
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reg_val |= Uart_en_mask;
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write32(reg, reg_val);
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uart_branch_clk_enable_reg(gsbi_port);
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}
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/**
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* uart_set_gsbi_clk - enables HCLK for UART GSBI port
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*/
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static void uart_set_gsbi_clk(unsigned int gsbi_port)
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{
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setbits_le32(GSBIn_HCLK_CTL_REG(gsbi_port), BIT(4));
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}
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/**
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* uart_clock_config - configures UART clocks
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*
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* Configures GSBI UART dividers, enable root and branch clocks.
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*/
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void uart_clock_config(unsigned int gsbi_port, unsigned int m,
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unsigned int n, unsigned int d, unsigned int clk_dummy)
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{
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uart_set_rate_mnd(gsbi_port, m, d);
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uart_pll_vote_clk_enable(clk_dummy);
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uart_local_clock_enable(gsbi_port, n, m);
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uart_set_gsbi_clk(gsbi_port);
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}
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/**
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* nand_clock_config - configure NAND controller clocks
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*
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* Enable clocks to EBI2. Must be invoked before touching EBI2
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* registers.
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*/
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void nand_clock_config(void)
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{
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write32(EBI2_CLK_CTL_REG,
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CLK_BRANCH_ENA(1) | ALWAYS_ON_CLK_BRANCH_ENA(1));
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/* Wait for clock to stabilize. */
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udelay(10);
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}
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/**
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* usb_clock_config - configure USB controller clocks and reset the controller
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*/
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void usb_clock_config(void)
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{
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/* Magic clock initialization numbers, nobody knows how they work... */
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write32(USB30_MASTER_CLK_CTL_REG, 0x10);
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write32(USB30_1_MASTER_CLK_CTL_REG, 0x10);
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write32(USB30_MASTER_CLK_MD, 0x500DF);
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write32(USB30_MASTER_CLK_NS, 0xE40942);
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write32(USB30_MOC_UTMI_CLK_MD, 0x100D7);
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write32(USB30_MOC_UTMI_CLK_NS, 0xD80942);
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write32(USB30_MOC_UTMI_CLK_CTL, 0x10);
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write32(USB30_1_MOC_UTMI_CLK_CTL, 0x10);
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write32(USB30_RESET,
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1 << 5 | /* assert port2 HS PHY async reset */
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1 << 4 | /* assert master async reset */
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1 << 3 | /* assert sleep async reset */
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1 << 2 | /* assert MOC UTMI async reset */
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1 << 1 | /* assert power-on async reset */
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1 << 0); /* assert PHY async reset */
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udelay(5);
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write32(USB30_RESET, 0); /* deassert all USB resets again */
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}
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