227 lines
6.0 KiB
C
227 lines
6.0 KiB
C
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/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* UART module for ISH */
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#ifndef __CROS_EC_UART_DEFS_H_
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#define __CROS_EC_UART_DEFS_H_
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#include <stdint.h>
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#include <stddef.h>
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#define UART_ERROR -1
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#define UART_BUSY -2
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#define HSU_BASE ISH_UART_BASE
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#define UART0_OFFS (0x80)
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#define UART0_BASE (ISH_UART_BASE + UART0_OFFS)
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#define UART0_SIZE (0x80)
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#define UART1_OFFS (0x100)
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#define UART1_BASE (ISH_UART_BASE + UART1_OFFS)
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#define UART1_SIZE (0x80)
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#define UART2_OFFS (0x180)
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#define UART2_BASE (ISH_UART_BASE + UART2_OFFS)
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#define UART2_SIZE (0x80)
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#define UART_REG(size, name, n) \
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REG##size(uart_ctx[n].base + \
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UART_OFFSET_##name * uart_ctx[n].addr_interval)
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/* Register accesses */
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#define LSR(n) UART_REG(8, LSR, n)
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#define THR(n) UART_REG(8, THR, n)
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#define FOR(n) UART_REG(32, FOR, n)
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#define RBR(n) UART_REG(8, RBR, n)
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#define DLL(n) UART_REG(8, DLL, n)
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#define DLH(n) UART_REG(8, DLH, n)
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#define DLD(n) UART_REG(8, DLD, n)
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#define IER(n) UART_REG(8, IER, n)
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#define IIR(n) UART_REG(8, IIR, n)
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#define FCR(n) UART_REG(8, FCR, n)
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#define LCR(n) UART_REG(8, LCR, n)
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#define MCR(n) UART_REG(8, MCR, n)
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#define MSR(n) UART_REG(8, MSR, n)
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#define ABR(n) UART_REG(32, ABR, n)
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#define PS(n) UART_REG(32, PS, n)
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#define MUL(n) UART_REG(32, MUL, n)
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#define DIV(n) UART_REG(32, DIV, n)
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/* RBR: Receive Buffer register (BLAB bit = 0) */
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#define UART_OFFSET_RBR (0)
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/* THR: Transmit Holding register (BLAB bit = 0) */
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#define UART_OFFSET_THR (0)
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/* IER: Interrupt Enable register (BLAB bit = 0) */
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#define UART_OFFSET_IER (1)
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#define FCR_FIFO_SIZE_16 (0x00)
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#define FCR_FIFO_SIZE_64 (0x20)
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#define FCR_ITL_FIFO_64_BYTES_1 (0x00)
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/* FCR: FIFO Control register */
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#define UART_OFFSET_FCR (2)
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#define FCR_FIFO_ENABLE BIT(0)
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#define FCR_RESET_RX BIT(1)
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#define FCR_RESET_TX BIT(2)
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/* LCR: Line Control register */
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#define UART_OFFSET_LCR (3)
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#define LCR_DLAB (0x80)
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#define LCR_5BIT_CHR (0x00)
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#define LCR_6BIT_CHR (0x01)
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#define LCR_7BIT_CHR (0x02)
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#define LCR_8BIT_CHR (0x03)
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#define LCR_BIT_CHR_MASK (0x03)
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#define LCR_SB (0x40) /* Set Break */
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/* MCR: Modem Control register */
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#define UART_OFFSET_MCR (4)
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#define MCR_DTR BIT(0)
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#define MCR_RTS BIT(1)
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#define MCR_LOO BIT(4)
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#define MCR_INTR_ENABLE BIT(3)
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#define MCR_AUTO_FLOW_EN BIT(5)
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/* LSR: Line Status register */
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#define UART_OFFSET_LSR (5)
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#define LSR_DR BIT(0) /* Data Ready */
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#define LSR_OE BIT(1) /* Overrun error */
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#define LSR_PE BIT(2) /* Parity error */
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#define LSR_FE BIT(3) /* Framing error */
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#define LSR_BI BIT(4) /* Breaking interrupt */
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#define LSR_THR_EMPTY BIT(5) /* Non FIFO mode: Transmit holding
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* register empty
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*/
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#define LSR_TDRQ BIT(5) /* FIFO mode: Transmit Data request */
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#define LSR_TEMT BIT(6) /* Transmitter empty */
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#define FCR_ITL_FIFO_64_BYTES_56 (BIT(6) | BIT(7))
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#define IER_RECV BIT(0)
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#define IER_TDRQ BIT(1)
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#define IER_LINE_STAT BIT(2)
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#define UART_OFFSET_IIR (2)
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/* MSR: Modem Status register */
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#define UART_OFFSET_MSR (6)
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/* DLL: Divisor Latch Reg. low byte (BLAB bit = 1) */
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#define UART_OFFSET_DLL (0)
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/* DLH: Divisor Latch Reg. high byte (BLAB bit = 1) */
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#define UART_OFFSET_DLH (1)
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/* DLH: Divisor Latch Fractional. (BLAB bit = 1) */
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#define UART_OFFSET_DLD (2)
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/* FOR: Fifo O Register (ISH only) */
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#define UART_OFFSET_FOR (0x20)
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#define FOR_OCCUPANCY_OFFS 0
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#define FOR_OCCUPANCY_MASK 0x7F
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/* ABR: Auto-Baud Control Register (ISH only) */
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#define UART_OFFSET_ABR (0x24)
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#define ABR_UUE BIT(4)
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/* Pre-Scalar Register (ISH only) */
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#define UART_OFFSET_PS (0x30)
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/* DDS registers (ISH only) */
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#define UART_OFFSET_MUL (0x34)
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#define UART_OFFSET_DIV (0x38)
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/* G_IEN: Global Interrupt Enable (ISH only) */
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#define HSU_REG_GIEN REG32(HSU_BASE + 0x0)
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#define HSU_REG_GIST REG32(HSU_BASE + 0x4)
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#define GIEN_PWR_MGMT BIT(24)
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#define GIEN_DMA_EN BIT(5)
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#define GIEN_UART2_EN BIT(2)
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#define GIEN_UART1_EN BIT(1)
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#define GIEN_UART0_EN BIT(0)
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#define GIST_DMA_EN BIT(5)
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#define GIST_UART2_EN BIT(2)
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#define GIST_UART1_EN BIT(1)
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#define GIST_UART0_EN BIT(0)
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#define GIST_UARTx_EN (GIST_UART0_EN|GIST_UART1_EN|GIST_UART2_EN)
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/* UART config flag, send to sc_io_control if the current UART line has HW
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* flow control lines connected.
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*/
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#define UART_CONFIG_HW_FLOW_CONTROL BIT(0)
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/* UART config flag for sc_io_control. If defined a sc_io_event_rx_msg is
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* raised only when the rx buffer is completely full. Otherwise, the event
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* is raised after a timeout is received on the UART line,
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* and all data received until now is provided.
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*/
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#define UART_CONFIG_DELIVER_FULL_RX_BUF BIT(1)
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/* UART config flag for sc_io_control. If defined a sc_io_event_rx_buf_depleted
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* is raised when all rx buffers that were added are full. Otherwise, no
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* event is raised.
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*/
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#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF BIT(2)
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#define UART_INT_DEVICES 3
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#define UART_EXT_DEVICES 8
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#define UART_DEVICES UART_INT_DEVICES
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#define UART_ISH_ADDR_INTERVAL 1
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#define B9600 0x0000d
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#define B57600 0x00000018
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#define B115200 0x00000011
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#define B921600 0x00000012
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#define B2000000 0x00000013
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#define B3000000 0x00000014
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#define B3250000 0x00000015
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#define B3500000 0x00000016
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#define B4000000 0x00000017
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#define B19200 0x0000e
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#define B38400 0x0000f
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/* KHZ, MHZ */
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#define KHZ(x) ((x) * 1000)
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#define MHZ(x) (KHZ(x) * 1000)
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#if defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5)
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#define UART_ISH_INPUT_FREQ MHZ(120)
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#elif defined(CHIP_FAMILY_ISH4)
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#define UART_ISH_INPUT_FREQ MHZ(100)
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#endif
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#define UART_DEFAULT_BAUD_RATE 115200
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#define UART_STATE_CG BIT(UART_OP_CG)
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enum UART_PORT {
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UART_PORT_0,
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UART_PORT_1,
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UART_PORT_MAX
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};
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enum UART_OP {
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UART_OP_READ,
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UART_OP_WRITE,
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UART_OP_CG,
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UART_OP_MAX
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};
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enum {
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BAUD_IDX,
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BAUD_SPEED,
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BAUD_TABLE_MAX
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};
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struct uart_ctx {
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uint32_t id;
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uint32_t base;
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uint32_t addr_interval;
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uint32_t uart_state;
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uint32_t is_open;
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uint32_t baud_rate;
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uint32_t input_freq;
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uint32_t client_flags;
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};
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#endif /* _CROS_EC_UART_DEFS_H_ */
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