170 lines
4.7 KiB
Markdown
170 lines
4.7 KiB
Markdown
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# Squared
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## Overview
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### Top
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![][overview_top]
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### Bottom
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![][overview_bottom]
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* **Legend**
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* [BLUE][header_cn16_link]: UART0 / USB connector
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* [GREEN][header_gpio_link]: UART1 / GPIO header
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* [RED][header_cn22_link]: SPI header
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* YELLOW: Indicates pin 1
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## Mainboard components
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### Platform
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```eval_rst
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+------------------+----------------------------------+
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| CPU | Intel Atom, Celeron, Pentium |
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+------------------+----------------------------------+
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| PCH | Intel Apollo Lake |
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+------------------+----------------------------------+
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| EC / Super IO | N/A |
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+------------------+----------------------------------+
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| Coprocessor | Intel TXE 3.0 |
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+------------------+----------------------------------+
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```
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### Flash chip
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```eval_rst
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+---------------------+------------+
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| Type | Value |
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+=====================+============+
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| Socketed flash | no |
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+---------------------+------------+
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| Vendor | Winbond |
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+---------------------+------------+
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| Model | W25Q128FW |
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+---------------------+------------+
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| Voltage | 1.8V |
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+---------------------+------------+
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| Size | 16 MiB |
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+---------------------+------------+
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| Package | SOIC-8 |
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+---------------------+------------+
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| Write protection | No |
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+---------------------+------------+
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| Internal flashing | No |
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+---------------------+------------+
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| In curcuit flashing | Yes |
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+---------------------+------------+
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```
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### Debugging
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#### UART0 (CN16)
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This connector is located on the **bottom** side (see [here][overview_bottom_link]).
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![][header_cn16]
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#### UART1 (GPIO header)
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The GPIO header is located on the **bottom** side (see [here][overview_bottom_link]).
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![][header_gpio]
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## Building and flashing coreboot
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### Using the SPI header
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The SPI header is located on the **bottom** side (see [here][overview_bottom_link]).
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![][header_cn22]
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### Preperations
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In order to build coreboot, it's neccessary to extract some files from the vendor firmware. Make sure that you have a fully working dump.
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```bash
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[upsquared]$ ls
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firmware_vendor.rom
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```
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```bash
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[upsquared]$ mkdir extracted && cd extracted
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[extracted]$ ifdtool -x ../firmware_vendor.rom
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File ../firmware_vendor.rom is 16777216 bytes
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Peculiar firmware descriptor, assuming Ibex Peak compatibility.
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Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
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Flash Region 1 (BIOS): 00001000 - 00efefff
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Flash Region 2 (Intel ME): 07fff000 - 00000fff (unused)
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Flash Region 3 (GbE): 07fff000 - 00000fff (unused)
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Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused)
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Flash Region 5 (Reserved): 00eff000 - 00ffefff
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Flash Region 6 (Reserved): 07fff000 - 00000fff (unused)
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Flash Region 7 (Reserved): 07fff000 - 00000fff (unused)
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Flash Region 8 (EC): 07fff000 - 00000fff (unused)
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```
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```bash
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flashregion_0_flashdescriptor.bin
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flashregion_1_bios.bin
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flashregion_5_reserved.bin
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```
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### Clean up
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```bash
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[coreboot]$ make distclean
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```
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### Configuring
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```bash
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[coreboot]$ touch .config
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[coreboot]$ ./util/scripts/config --enable VENDOR_UP
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[coreboot]$ ./util/scripts/config --enable BOARD_UP_SQUARED
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[coreboot]$ ./util/scripts/config --enable NEED_IFWI
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[coreboot]$ ./util/scripts/config --enable HAVE_IFD_BIN
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[coreboot]$ ./util/scripts/config --set-str IFWI_FILE_NAME "<flashregion_1_bios.bin>"
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[coreboot]$ ./util/scripts/config --set-str IFD_BIN_PATH "<flashregion_0_flashdescriptor.bin>"
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[coreboot]$ make olddefconfig
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```
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### Building
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```bash
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[coreboot]$ make
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```
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Now you should have a working and ready to use coreboot build at `build/coreboot.rom`.
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### Flashing
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```bash
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[coreboot]$ flashrom -p <your_programmer> -w build/coreboot.rom
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```
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## Board status
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### Working
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- bootblock, romstage, ramstage
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- Serial console UART0, UART1
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- SPI flash console
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- iGPU init with libgfxinit
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- LAN1, LAN2
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- USB2, USB3
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- HDMI, DisplayPort
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- eMMC
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- flashing with flashrom externally
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### Work in progress
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- Documentation
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- ACPI
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### Not working / Known issues
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- Generally SeaBIOS works, but it can't find the CBFS region and therefore it can't load seavgabios. This is because of changes at the Apollolake platform.
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### Untested
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- GPIO pin header
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- 60 pin EXHAT
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- Camera interface
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- MIPI-CSI2 2-lane (2MP)
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- MIPI-CSI2 4-lane (8MP)
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- SATA3
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- USB3 OTG
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- embedded DisplayPort
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- M.2 slot
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- mini PCIe
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- flashing with flashrom internally using Linux
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[header_cn16]: header_cn16_10pin_uart0.svg
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[header_cn16_link]: #uart0-cn16
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[header_cn22]: header_cn22_12pin_spi.svg
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[header_cn22_link]: #using-the-spi-header
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[header_gpio]: header_40pin_gpio_uart1.svg
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[header_gpio_link]: #uart1-gpio-header
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[overview_top]: top.jpg
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[overview_bottom]: bottom.jpg
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[overview_bottom_link]: #bottom
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