136 lines
3.8 KiB
C
136 lines
3.8 KiB
C
/* Copyright 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Watchdog driver */
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#include "common.h"
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#include "cpu.h"
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#include "hooks.h"
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#include "hwtimer_chip.h"
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#include "panic.h"
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#include "registers.h"
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#include "task.h"
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#include "watchdog.h"
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/* Panic data goes at the end of RAM. */
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static struct panic_data * const pdata_ptr = PANIC_DATA_PTR;
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/* Enter critical period or not. */
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static int wdt_warning_fired;
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/*
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* We use WDT_EXT_TIMER to trigger an interrupt just before the watchdog timer
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* will fire so that we can capture important state information before
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* being reset.
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*/
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/* Magic value to tickle the watchdog register. */
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#define ITE83XX_WATCHDOG_MAGIC_WORD 0x5C
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/* Start to print warning message. */
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#define ITE83XX_WATCHDOG_WARNING_MS CONFIG_AUX_TIMER_PERIOD_MS
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/* The interval to print warning message at critical period. */
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#define ITE83XX_WATCHDOG_CRITICAL_MS 30
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/* set warning timer */
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static void watchdog_set_warning_timer(int32_t ms, int init)
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{
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ext_timer_ms(WDT_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 1, ms, init, 0);
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}
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void watchdog_warning_irq(void)
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{
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#ifdef CONFIG_SOFTWARE_PANIC
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#if defined(CHIP_CORE_NDS32)
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pdata_ptr->nds_n8.ipc = get_ipc();
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#elif defined(CHIP_CORE_RISCV)
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pdata_ptr->riscv.mepc = get_mepc();
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#endif
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#endif
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/* clear interrupt status */
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task_clear_pending_irq(et_ctrl_regs[WDT_EXT_TIMER].irq);
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/* Reset warning timer. */
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IT83XX_ETWD_ETXCTRL(WDT_EXT_TIMER) = 0x03;
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#if defined(CHIP_CORE_NDS32)
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/*
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* The IPC (Interruption Program Counter) is the shadow stack register
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* of the PC (Program Counter). It stores the return address of program
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* (PC->IPC) when the ISR was called.
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*
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* The LP (Link Pointer) stores the program address of the next
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* sequential instruction for function call return purposes.
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* LP = PC+4 after a jump and link instruction (jal).
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*/
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panic_printf("Pre-WDT warning! IPC:%08x LP:%08x TASK_ID:%d\n",
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get_ipc(), ilp, task_get_current());
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#elif defined(CHIP_CORE_RISCV)
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panic_printf("Pre-WDT warning! MEPC:%08x RA:%08x TASK_ID:%d\n",
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get_mepc(), ira, task_get_current());
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#endif
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if (!wdt_warning_fired++)
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/*
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* Reduce interval of warning timer, so we can print more
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* warning messages during critical period.
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*/
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watchdog_set_warning_timer(ITE83XX_WATCHDOG_CRITICAL_MS, 0);
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}
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void watchdog_reload(void)
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{
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/* Reset warning timer. */
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IT83XX_ETWD_ETXCTRL(WDT_EXT_TIMER) = 0x03;
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/* Restart (tickle) watchdog timer. */
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IT83XX_ETWD_EWDKEYR = ITE83XX_WATCHDOG_MAGIC_WORD;
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if (wdt_warning_fired) {
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wdt_warning_fired = 0;
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/* Reset warning timer to default if watchdog is touched. */
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watchdog_set_warning_timer(ITE83XX_WATCHDOG_WARNING_MS, 0);
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}
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}
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DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
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int watchdog_init(void)
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{
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uint16_t wdt_count = CONFIG_WATCHDOG_PERIOD_MS * 1024 / 1000;
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/* Unlock access to watchdog registers. */
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IT83XX_ETWD_ETWCFG = 0x00;
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/* Set WD timer to use 1.024kHz clock. */
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IT83XX_ETWD_ET1PSR = 0x01;
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/* Set WDT key match enabled and WDT clock to use ET1PSR. */
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IT83XX_ETWD_ETWCFG = 0x30;
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#ifdef CONFIG_HIBERNATE
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/* bit4: watchdog can be stopped. */
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IT83XX_ETWD_ETWCTRL |= BIT(4);
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#else
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/* Specify that watchdog cannot be stopped. */
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IT83XX_ETWD_ETWCTRL = 0x00;
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#endif
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/* Start WDT_EXT_TIMER (CONFIG_AUX_TIMER_PERIOD_MS ms). */
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watchdog_set_warning_timer(ITE83XX_WATCHDOG_WARNING_MS, 1);
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/* Start timer 1 (must be started for watchdog timer to run). */
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IT83XX_ETWD_ET1CNTLLR = 0x00;
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/*
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* Set watchdog timer to CONFIG_WATCHDOG_PERIOD_MS ms.
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* Writing CNTLL starts timer.
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*/
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IT83XX_ETWD_EWDCNTLHR = (wdt_count >> 8) & 0xff;
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IT83XX_ETWD_EWDCNTLLR = wdt_count & 0xff;
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/* Lock access to watchdog registers. */
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IT83XX_ETWD_ETWCFG = 0x3f;
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return EC_SUCCESS;
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}
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