43 lines
1.2 KiB
C
43 lines
1.2 KiB
C
/* Copyright 2018 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Icelake chipset power control module for Chrome EC */
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#ifndef __CROS_EC_ICELAKE_H
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#define __CROS_EC_ICELAKE_H
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/* Input state flags. */
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#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
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#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
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#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
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#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
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IN_PCH_SLP_S4_DEASSERTED | \
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IN_PCH_SLP_SUS_DEASSERTED)
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#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_DSW_DPWROK)
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#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
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#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED
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#define CHARGER_INITIALIZED_DELAY_MS 100
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#define CHARGER_INITIALIZED_TRIES 40
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/* Power signals list */
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enum power_signal {
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X86_SLP_S0_DEASSERTED,
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X86_SLP_S3_DEASSERTED,
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X86_SLP_S4_DEASSERTED,
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X86_SLP_SUS_DEASSERTED,
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X86_RSMRST_L_PGOOD,
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X86_DSW_DPWROK,
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/* Number of X86 signals */
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POWER_SIGNAL_COUNT
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};
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#endif /* __CROS_EC_ICELAKE_H */
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