85 lines
2.1 KiB
Markdown
85 lines
2.1 KiB
Markdown
# Elgon
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This page describes how to run coreboot on the [Elgon] compute board
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from [OpenCellular].
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## TODO
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* Add hard reset control
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## Flashing coreboot
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```eval_rst
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+---------------------+------------+
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| Type | Value |
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+=====================+============+
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| Socketed flash | no |
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+---------------------+------------+
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| Model | W25Q128 |
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+---------------------+------------+
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| Size | 16 MiB |
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+---------------------+------------+
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| In circuit flashing | yes |
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+---------------------+------------+
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| Package | SOIC-8 |
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+---------------------+------------+
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| Write protection | No |
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+---------------------+------------+
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| Dual BIOS feature | No |
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+---------------------+------------+
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| Internal flashing | yes |
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+---------------------+------------+
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```
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### Internal programming
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The SPI flash can be accessed using [flashrom].
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### External programming
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The EVT board does have a pinheader to flash the SOIC-8 in circuit.
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Directly connecting a Pomona test-clip on the flash is also possible.
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**Total board view of EVT**
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![][elgon1]
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[elgon1]: elgon1.jpg
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**Closeup view of SOIC-8 flash IC and USB serial connector of EVT (marked blue)**
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![][elgon2]
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[elgon2]: elgon2.jpg
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**SPI header (marked blue)**
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![][elgon_conn_j9_pcb]
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[elgon_conn_j9_pcb]: elgon_conn_j9_pcb.jpg
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**SPI header pinout**
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Dediprog compatible pinout.
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![][elgon_conn_j9]
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[elgon_conn_j9]: elgon_conn_j9.png
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## Technology
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```eval_rst
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+---------------+----------------------------------------+
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| SoC | :doc:`../../soc/cavium/cn81xx/index` |
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+---------------+----------------------------------------+
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| CPU | Cavium ARMv8-Quadcore `CN81XX`_ |
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+---------------+----------------------------------------+
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.. _CN81XX: https://www.cavium.com/product-octeon-tx-cn80xx-81xx.html
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```
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[Elgon]: https://github.com/Telecominfraproject/OpenCellular
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[OpenCellular]: https://code.fb.com/connectivity/introducing-opencellular-an-open-source-wireless-access-platform/
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[flashrom]: https://flashrom.org/Flashrom
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