268 lines
7.8 KiB
Markdown
268 lines
7.8 KiB
Markdown
coreboot 4.9 release notes
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==========================
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The 4.9 release covers commit 532b8d5f25 to commit 7f520c8fe6
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There is a pgp signed 4.9 tag in the git repository, and a branch will
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be created as needed.
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In the little more than 7 months since 4.8.1 we had 175 authors commit
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2610 changes to master. The changes were, for the most part, all over
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the place, touching every part of the repository: chipsets, mainboards,
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tools, build system, documentation.
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In that time we also had 70 authors made their first commit to coreboot:
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Welcome and to many more!
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Finally, a big Thank You to all contributors who helped shape the
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coreboot project, community and code with their effort, no matter if
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through development, review, testing, documentation or by helping people
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asking questions on our venues like IRC or our mailing list.
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Clean up
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--------
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If there's any topic to give to this release, "clean up" might be the
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most appropriate: There was lots of effort to bring the codebase into
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compliance with our coding style, to remove old idioms that we'd like
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to retire like the overloaded `device_t` data type, and to let features
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percolate through the entire tree to bring more uniformity to its parts.
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For example, during the coreboot 4.4 cycle, coreboot gained the notion
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of mainboard variants to avoid duplication of code in rather similar
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mainboards.
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Back then, this feature was developed and used mostly for the benefit
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of Chrome OS devices, but more recently the code for various Lenovo
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Thinkpads was deduplicated in the same way.
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Another part of cleaning up our tree is improving our tools that help
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developers follow coding style and avoid mistakes, as well as the
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infrastructure we have for automated build tests and we've seen quite
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some activity in that space as well.
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Documentation
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-------------
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Since the last release we also moved the documentation into the
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repository. No need for a special wiki account to edit the documentation,
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and by colocating sources and documentation, it's easier to keep the
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latter in sync with the code, too.
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This effort is still under way, which is why we still host the old wiki (now
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read-only) in parallel to the [new documentation
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site](https://doc.coreboot.org) that is rendered from coreboot.git's
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Documentation/ directory.
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Blobs handling
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--------------
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Another big change is in our blobs handling: Given that Intel now
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provides a reasonably licensed repository with FSP binaries, we were
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able to mirror it to coreboot.org and integrate it in the build system.
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This makes it easier to have working images out of the box for devices
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that depend on Intel's proprietary init code.
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As usual the blobs aren't part of the coreboot tree and only downloaded
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with the `USE_BLOBS` options.
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Deprecations
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------------
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One of the first changes to coreboot after the 4.8 release was to remove
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boards that didn't support certain new features and were apparently
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unmaintained, as discussed in the release notes of coreboot 4.6.
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We didn't follow up on all plans made back then to deprecate boards more
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aggressively: The board status reporting mechanism is still rather raw
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and therefore places quite a burden on otherwise sympathetic contributors
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of build results.
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Also, there will be no deprecations after 4.10: Due to its slipping
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schedule, coreboot 4.9 is released rather late, and as a result 4.10
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will only see about 4 months of development. We considered that a rather
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short timeframe in which to bring old boards up to new standards, and
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so the next deprecation cycle may be announced with 4.10 to occur after
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4.11 is released, in late 2019.
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General changes
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---------------
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* Various code cleanups
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* Removed `device_t` in favor of `struct device*` in ramstage code
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* Removed unnecessary include directives
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* Improved adherence to coding style
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* Deduplicated boards by using the variants mechanism
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* Expand use of the postcar stage
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* Add bootblock compression capability: on systems that copy the bootblock
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from very slow flash to SRAM, allow adding a stub that decompresses the
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bootblock into SRAM to minimize the amount of flash reads
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* Rename the POWER8 architecture port to PPC64 to reflect that it isn't limited
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to POWER8
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* Added support for booting FIT (uImage) payloads on arm64
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* Added SPI flash write protection API
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* Implemented on Winbond
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* Implemented TCPA log for measured boot
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* Implemented GDB support for arm64 architecture in libpayload
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* Dropped support for unmaintained code paths
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* Measured boot support
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Added 56 mainboards
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-------------------
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* ASROCK G41C-GS
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* ASROCK G41M-GS
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* ASROCK G41M-S3
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* ASROCK G41M-VS3 R2.0
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* ASROCK H81M-HDS
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* ASUS P5QC
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* ASUS P5QL-PRO
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* ASUS P5Q-PRO
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* ASUS P8H61-M-LX
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* ASUS P8H61-M-PRO
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* CAVIUM CN8100-SFF-EVB
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* FACEBOOK WATSON
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* FOXCONN D41S
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* GIGABYTE GA-H61M-S2PV
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* GOOGLE ALEENA
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* GOOGLE AMPTON
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* GOOGLE ARCADA
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* GOOGLE ASUKA
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* GOOGLE BOBBA
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* GOOGLE BUDDY
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* GOOGLE CAREENA
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* GOOGLE CAROLINE
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* GOOGLE CASTA
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* GOOGLE CAVE
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* GOOGLE DELAN
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* GOOGLE DRAGONEGG
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* GOOGLE FLEEX
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* GOOGLE HATCH
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* GOOGLE KARMA
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* GOOGLE KUKUI
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* GOOGLE LIARA
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* GOOGLE MEEP
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* GOOGLE RAMMUS
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* GOOGLE SARIEN
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* GOOGLE SENTRY
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* HEWLETT PACKARD HP COMPAQ 8200 ELITE SFF PC
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* INTEL COFFEELAKE RVP11
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* INTEL COFFEELAKE RVP8
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* INTEL COFFEELAKE RVPU
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* INTEL DG41WV
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* INTEL ICELAKE RVPU
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* INTEL ICELAKE RVPY
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* INTEL WHISKEYLAKE RVP
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* LENOVO T431S
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* LENOVO THINKCENTRE A58
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* LENOVO W500
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* LENOVO W530
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* OPENCELLULAR ELGON
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* OPENCELLULAR ROTUNDU
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* OPENCELLULAR SUPABRCKV1
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* SIEMENS MC-APL2
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* SIEMENS MC-APL3
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* SIEMENS MC-APL4
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* SIEMENS MC-APL5
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Dropped 71 mainboards
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---------------------
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* AAEON PFM-540I REVB
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* AMD DB800
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* AMD DBM690T
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* AMD F2950
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* AMD MAHOGANY
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* AMD NORWICH
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* AMD PISTACHIO
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* AMD SERENGETI-CHEETAH
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* ARTECGROUP DBE61
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* ASROCK 939A785GMH
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* ASUS A8N-E
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* ASUS A8N-SLI
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* ASUS A8V-E DELUXE
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* ASUS A8V-E SE
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* ASUS K8V-X
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* ASUS KFSN4-DRE K8
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* ASUS M2N-E
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* ASUS M2V
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* ASUS M2V MX-SE
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* BACHMANN OT200
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* BCOM WINNETP680
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* BROADCOM BLAST
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* DIGITALLOGIC MSM800SEV
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* GIGABYTE GA-2761GXDK
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* GIGABYTE M57SLI
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* GOOGLE KAHLEE
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* GOOGLE MEOWTH
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* GOOGLE PURIN
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* GOOGLE ROTOR
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* GOOGLE ZOOMBINI
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* HP DL145-G1
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* HP DL145-G3
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* IEI PCISA LX-800 R10
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* IEI PM LX2-800 R10
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* IEI PM LX-800 R11
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* INTEL COUGAR-CANYON2
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* INTEL STARGO2
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* IWILL DK8 HTX
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* JETWAY J7F2
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* JETWAY J7F4K1G2E
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* JETWAY J7F4K1G5D
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* KONTRON KT690
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* LINUTOP LINUTOP1
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* LIPPERT HURRICANE LX
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* LIPPERT LITERUNNER LX
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* LIPPERT ROADRUNNER LX
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* LIPPERT SPACERUNNER LX
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* LOWRISC NEXYS4DDR
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* MSI MS7135
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* MSI MS7260
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* MSI MS9185
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* MSI MS9282
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* NVIDIA L1-2PVV
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* SIEMENS SITEMP-G1P1
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* SUNW ULTRA40
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* SUNW ULTRA40M2
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* SUPERMICRO H8DME
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* SUPERMICRO H8DMR
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* TECHNEXION TIM5690
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* TECHNEXION TIM8690
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* TRAVERSE GEOS
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* TYAN S2912
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* VIA EPIA-CN
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* VIA EPIA-M700
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* VIA PC2500E
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* VIA VT8454C
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* WINENT MB6047
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* WINENT PL6064
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* WINNET G170
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CPU changes
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-----------
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* cpu/intel/model\_2065x,206ax,haswell: Switch to `POSTCAR_STAGE`
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* cpu/intel/slot\_1: Switch to different CAR setup
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* Dropped support for the FSP1.0 sandy-/ivy-bridge bootpath
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SoC changes
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-----------
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* Added Cavium CN81xx, Intel Ice Lake and Mediatek MT8183
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* Dropped Broadcom Cygnus, Lowrisc and Marvell mvmap2315
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Northbridge changes
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-------------------
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* Dropped AMD K8, VIA CN700, VIA CX700, VIA VX800 because they lack `EARLY_CBMEM` support
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* intel/e7505: Moved to `EARLY_CBMEM`
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* nb/intel/i945,e7505,pineview,x4x,gm45,i440bx: Moved to `POSTCAR_STAGE`
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* nb/intel/i440bx, e7505: Moved to `RELOCATABLE_RAMSTAGE`
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* intel/x4x: Add DDR3 support
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* nb/intel/pineview: Speed up fetching SPD
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* nb/intel/i945,gm45,x4x,pineview: Use TSEG in SMI
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Southbridge changes
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-------------------
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* sb/intel/i82801{g,i,j}x, lynxpoint: Use the common ACPI pirq generator
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* sb/intel/i82801{g,i,j}x: Use common code to set up SMM and for the smihandler
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* Use common functions for PMBASE configuration
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Payload changes
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---------------
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* Support initrd in uImage/FIT to be placed above 4GiB
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* Added documentation for uImage/FIT payloads
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Toolchain
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---------
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* Update to gcc 8.1.0, binutils 2.30, IASL 20180810, clang 6
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