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coreboot/i945 Thinkpads: replace dd commands with INTEL_ADD_TOP_SWAP_BOOTBLOCK 

It is possible to install GNU Boot on I945 Thinkpads without opening
the computer even if the nonfree bios sets the bootblock region (the
last 64K of the flash chip) read-only.

The flash chip looks like that:
+-----   -----+---------------------------+-------------------------+
|     ...     | Secondary bootblock (64k) | Primary bootblock (64k) |
+-----   -----+---------------------------+-------------------------+
0      0x1e0000                                                  2MiB

To bypass the read-only restriction we use an utility (bucts) that
tells the hardware to swap the primary bootblock with the secondary
one for the next boot. We then have to disable that swap and reflash
again.

CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK generates the two bootblocks
directly in coreboot so we don't need to use special commands to do
that anymore.

In addition the MacBook 1.1 and 2.1 are known not to have such
read-only restrictions so they don't need to have
CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK enabled.

Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org>
Acked-by: Adrien 'neox' Bourmault <neox@gnu.org>
This commit is contained in:
Denis 'GNUtoo' Carikli 2023-11-29 18:06:24 +01:00 committed by Adrien 'neox' Bourmault
parent 7bf153a207
commit 585f4d359a
Signed by: neox
GPG Key ID: 2974E1D5F25DFCC8
9 changed files with 8 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
resources/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb
View File

@ -240,7 +240,7 @@ CONFIG_AZALIA_MAX_CODECS=3
# CONFIG_PCIEXP_COMMON_CLOCK is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_UART_PCI_ADDR=0x0 CONFIG_UART_PCI_ADDR=0x0
CONFIG_INTEL_HAS_TOP_SWAP=y CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
# #

2
resources/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode
View File

@ -240,7 +240,7 @@ CONFIG_AZALIA_MAX_CODECS=3
# CONFIG_PCIEXP_COMMON_CLOCK is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_UART_PCI_ADDR=0x0 CONFIG_UART_PCI_ADDR=0x0
CONFIG_INTEL_HAS_TOP_SWAP=y CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
# #

2
resources/coreboot/t60_intelgpu/config/libgfxinit_corebootfb
View File

@ -240,7 +240,7 @@ CONFIG_AZALIA_MAX_CODECS=3
# CONFIG_PCIEXP_COMMON_CLOCK is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_UART_PCI_ADDR=0x0 CONFIG_UART_PCI_ADDR=0x0
CONFIG_INTEL_HAS_TOP_SWAP=y CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
# #

2
resources/coreboot/t60_intelgpu/config/libgfxinit_txtmode
View File

@ -240,7 +240,7 @@ CONFIG_AZALIA_MAX_CODECS=3
# CONFIG_PCIEXP_COMMON_CLOCK is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_UART_PCI_ADDR=0x0 CONFIG_UART_PCI_ADDR=0x0
CONFIG_INTEL_HAS_TOP_SWAP=y CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
# #

2
resources/coreboot/x60/config/libgfxinit_corebootfb
View File

@ -242,7 +242,7 @@ CONFIG_AZALIA_MAX_CODECS=3
# CONFIG_PCIEXP_COMMON_CLOCK is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_UART_PCI_ADDR=0x0 CONFIG_UART_PCI_ADDR=0x0
CONFIG_INTEL_HAS_TOP_SWAP=y CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
# #

2
resources/coreboot/x60/config/libgfxinit_txtmode
View File

@ -242,7 +242,7 @@ CONFIG_AZALIA_MAX_CODECS=3
# CONFIG_PCIEXP_COMMON_CLOCK is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_UART_PCI_ADDR=0x0 CONFIG_UART_PCI_ADDR=0x0
CONFIG_INTEL_HAS_TOP_SWAP=y CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
# #

2
resources/coreboot/x60_16mb/config/libgfxinit_corebootfb
View File

@ -242,7 +242,7 @@ CONFIG_AZALIA_MAX_CODECS=3
# CONFIG_PCIEXP_COMMON_CLOCK is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_UART_PCI_ADDR=0x0 CONFIG_UART_PCI_ADDR=0x0
CONFIG_INTEL_HAS_TOP_SWAP=y CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
# #

2
resources/coreboot/x60_16mb/config/libgfxinit_txtmode
View File

@ -242,7 +242,7 @@ CONFIG_AZALIA_MAX_CODECS=3
# CONFIG_PCIEXP_COMMON_CLOCK is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_UART_PCI_ADDR=0x0 CONFIG_UART_PCI_ADDR=0x0
CONFIG_INTEL_HAS_TOP_SWAP=y CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
# #

6
resources/packages/roms_helper/boot
View File

@ -252,12 +252,6 @@ moverom() {
dd if=descriptors/ich9m/ich9fdnogbe_${romsize}m.bin of=${newrompath} bs=1 count=4k conv=notrunc dd if=descriptors/ich9m/ich9fdnogbe_${romsize}m.bin of=${newrompath} bs=1 count=4k conv=notrunc
fi fi
done done
if [ "${cuttype}" = "i945 laptop" ]; then
dd if=${newrompath} of=top64k.bin bs=1 skip=$[$(stat -c %s ${newrompath}) - 0x10000] count=64k
dd if=top64k.bin of=${newrompath} bs=1 seek=$[$(stat -c %s ${newrompath}) - 0x20000] count=64k conv=notrunc
rm -f top64k.bin
fi
} }
# expected: configs must not specify a payload # expected: configs must not specify a payload