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Separate long listings

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Adrien Bourmault 2024-08-27 13:27:07 +02:00
parent 98023bd11e
commit 1912aa1afc
Signed by: neox
GPG Key ID: 57BC26A3687116F6
4 changed files with 1473 additions and 889 deletions
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hardware_init_review.pdf
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hardware_init_review.tex
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hardware_init_review.toc
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@ -1,8 +1,9 @@
\babel@toc {english}{}\relax
\contentsline {chapter}{Acknowledgments}{3}{chapter*.1}%
\contentsline {chapter}{Abstract}{4}{chapter*.2}%
\contentsline {chapter}{List of Figures}{7}{chapter*.2}%
\contentsline {chapter}{List of Listings}{8}{chapter*.2}%
\contentsline {chapter}{Contents}{5}{chapter*.3}%
\contentsline {chapter}{List of Figures}{7}{chapter*.4}%
\contentsline {chapter}{List of Listings}{9}{chapter*.5}%
\contentsline {chapter}{\numberline {1}Introduction to firmware and BIOS evolution}{10}{chapter.1}%
\contentsline {section}{\numberline {1.1}Historical context of BIOS}{10}{section.1.1}%
\contentsline {subsection}{\numberline {1.1.1}Definition and origin}{10}{subsection.1.1.1}%
@ -26,7 +27,7 @@
\contentsline {subsection}{\numberline {3.1.4}Payload}{27}{subsection.3.1.4}%
\contentsline {section}{\numberline {3.2}AMD Platform Security Processor and Intel Management Engine}{28}{section.3.2}%
\contentsline {chapter}{\numberline {4}Memory initialization and training}{30}{chapter.4}%
\contentsline {section}{\numberline {4.1}Importance of DDR3 Memory Initialization}{30}{section.4.1}%
\contentsline {section}{\numberline {4.1}Importance of DDR3 memory initialization}{30}{section.4.1}%
\contentsline {subsection}{\numberline {4.1.1}General steps for DDR3 configuration}{31}{subsection.4.1.1}%
\contentsline {section}{\numberline {4.2}Memory initialization techniques}{34}{section.4.2}%
\contentsline {subsection}{\numberline {4.2.1}Memory training algorithms}{34}{subsection.4.2.1}%
@ -36,29 +37,31 @@
\contentsline {subsubsection}{\numberline {4.2.2.3}Write leveling process}{37}{subsubsection.4.2.2.3}%
\contentsline {section}{\numberline {4.3}Current implementation and potential improvements}{39}{section.4.3}%
\contentsline {subsection}{\numberline {4.3.1}Current implementation in coreboot on the KGPE-D16}{39}{subsection.4.3.1}%
\contentsline {subsubsection}{\numberline {4.3.1.1}Details on the DQS training function}{48}{subsubsection.4.3.1.1}%
\contentsline {subsubsection}{\numberline {4.3.1.2}Details on the write leveling implementation}{51}{subsubsection.4.3.1.2}%
\contentsline {subsubsection}{\numberline {4.3.1.3}Details on the write leveling implementation}{54}{subsubsection.4.3.1.3}%
\contentsline {subsection}{\numberline {4.3.2}Write Leveling on AMD Fam15h G34 Processors with RDIMMs}{54}{subsection.4.3.2}%
\contentsline {subsubsection}{\numberline {4.3.2.1}Details on the DQS position training function}{55}{subsubsection.4.3.2.1}%
\contentsline {subsubsection}{\numberline {4.3.2.2}Details on the DQS receiver training function}{57}{subsubsection.4.3.2.2}%
\contentsline {subsection}{\numberline {4.3.3}Potential enhancements}{60}{subsection.4.3.3}%
\contentsline {subsubsection}{\numberline {4.3.3.1}DQS receiver training}{60}{subsubsection.4.3.3.1}%
\contentsline {subsubsection}{\numberline {4.3.3.2}Write leveling}{61}{subsubsection.4.3.3.2}%
\contentsline {subsection}{\numberline {4.3.4}DQS position training}{63}{subsection.4.3.4}%
\contentsline {subsection}{\numberline {4.3.5}On a wider scale...}{65}{subsection.4.3.5}%
\contentsline {subsubsection}{\numberline {4.3.5.1}Saving training values in NVRAM}{65}{subsubsection.4.3.5.1}%
\contentsline {subsubsection}{\numberline {4.3.5.2}A seedless DQS position training algorithm}{66}{subsubsection.4.3.5.2}%
\contentsline {chapter}{\numberline {5}Virtualization of the operating system through firmware abstraction}{68}{chapter.5}%
\contentsline {section}{\numberline {5.1}ACPI and abstraction of hardware control}{68}{section.5.1}%
\contentsline {section}{\numberline {5.2}SMM as a hidden execution layer}{69}{section.5.2}%
\contentsline {section}{\numberline {5.3}UEFI and persistence}{69}{section.5.3}%
\contentsline {subsection}{\numberline {5.3.1}Memory Management}{70}{subsection.5.3.1}%
\contentsline {subsection}{\numberline {5.3.2}File System Management}{70}{subsection.5.3.2}%
\contentsline {subsection}{\numberline {5.3.3}Device Drivers}{70}{subsection.5.3.3}%
\contentsline {subsection}{\numberline {5.3.4}Power Management}{70}{subsection.5.3.4}%
\contentsline {section}{\numberline {5.4}Intel and AMD: control beyond the OS}{70}{section.5.4}%
\contentsline {section}{\numberline {5.5}The OS as a virtualized environment}{71}{section.5.5}%
\contentsline {chapter}{Conclusion}{72}{chapter*.4}%
\contentsline {chapter}{Bibliography}{73}{chapter*.4}%
\contentsline {chapter}{GNU Free Documentation License}{80}{chapter*.6}%
\contentsline {subsubsection}{\numberline {4.3.1.1}Details on the DQS training function}{41}{subsubsection.4.3.1.1}%
\contentsline {subsubsection}{\numberline {4.3.1.2}Details on the write leveling implementation}{43}{subsubsection.4.3.1.2}%
\contentsline {subsubsection}{\numberline {4.3.1.3}Details on the write leveling implementation}{44}{subsubsection.4.3.1.3}%
\contentsline {subsection}{\numberline {4.3.2}Write Leveling on AMD Fam15h G34 Processors with RDIMMs}{44}{subsection.4.3.2}%
\contentsline {subsubsection}{\numberline {4.3.2.1}Details on the DQS position training function}{45}{subsubsection.4.3.2.1}%
\contentsline {subsubsection}{\numberline {4.3.2.2}Details on the DQS receiver training function}{48}{subsubsection.4.3.2.2}%
\contentsline {subsection}{\numberline {4.3.3}Potential enhancements}{50}{subsection.4.3.3}%
\contentsline {subsubsection}{\numberline {4.3.3.1}DQS receiver training}{50}{subsubsection.4.3.3.1}%
\contentsline {subsubsection}{\numberline {4.3.3.2}Write leveling}{52}{subsubsection.4.3.3.2}%
\contentsline {subsection}{\numberline {4.3.4}DQS position training}{54}{subsection.4.3.4}%
\contentsline {subsection}{\numberline {4.3.5}On a wider scale...}{56}{subsection.4.3.5}%
\contentsline {subsubsection}{\numberline {4.3.5.1}Saving training values in NVRAM}{56}{subsubsection.4.3.5.1}%
\contentsline {subsubsection}{\numberline {4.3.5.2}A seedless DQS position training algorithm}{57}{subsubsection.4.3.5.2}%
\contentsline {chapter}{\numberline {5}Virtualization of the operating system through firmware abstraction}{59}{chapter.5}%
\contentsline {section}{\numberline {5.1}ACPI and abstraction of hardware control}{59}{section.5.1}%
\contentsline {section}{\numberline {5.2}SMM as a hidden execution layer}{60}{section.5.2}%
\contentsline {section}{\numberline {5.3}UEFI and persistence}{60}{section.5.3}%
\contentsline {subsection}{\numberline {5.3.1}Memory Management}{61}{subsection.5.3.1}%
\contentsline {subsection}{\numberline {5.3.2}File System Management}{61}{subsection.5.3.2}%
\contentsline {subsection}{\numberline {5.3.3}Device Drivers}{61}{subsection.5.3.3}%
\contentsline {subsection}{\numberline {5.3.4}Power Management}{61}{subsection.5.3.4}%
\contentsline {section}{\numberline {5.4}Intel and AMD: control beyond the OS}{61}{section.5.4}%
\contentsline {section}{\numberline {5.5}The OS as a virtualized environment}{62}{section.5.5}%
\contentsline {chapter}{Conclusion}{63}{chapter*.6}%
\contentsline {chapter}{Bibliography}{70}{chapter*.7}%
\contentsline {chapter}{Appendix: Long code listings}{71}{chapter*.8}%
\contentsline {chapter}{GNU General Public License version 2}{82}{chapter*.9}%
\contentsline {chapter}{GNU Free Documentation License}{87}{chapter*.10}%

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packages.tex
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@ -41,7 +41,7 @@
\addtolength{\skip\footins}{0.6pc}
\renewcommand*\footnoterule{} %Footnode separator line
\def\siecle#1{\textsc{\romannumeral #1}\textsuperscript{e}~siècle}
%\def\siecle#1{\textsc{\romannumeral #1}\textsuperscript{e}~siècle}
\renewcommand{\cftsecleader}{\cftdotfill{\cftdotsep}} %places dots on sections lines as well