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Fix error and repetition in write leveling section

This commit is contained in:
Adrien Bourmault 2024-08-27 13:56:15 +02:00
parent d76a94b5a8
commit b23764ea21
Signed by: neox
GPG Key ID: 57BC26A3687116F6
1 changed files with 2 additions and 11 deletions
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hardware_init_review.tex
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@ -2657,17 +2657,8 @@ if (Pass == FirstPass) {
\label{lst:write_level_first_pass} \label{lst:write_level_first_pass}
\end{listing} \end{listing}
\subsubsection{Details on the write leveling implementation} The detailled write leveling process is divided into three
distinct phases, each managed by a specific function:
\subsection{Write Leveling on AMD Fam15h G34 Processors with RDIMMs}
Write leveling is a crucial process in memory initialization
for DDR3 systems, ensuring that the DQS signals are
correctly aligned with the clock signals during write
operations. This is particularly important in systems using
AMD Fam15h processors with G34 sockets and RDIMM. The
write leveling process is divided into three distinct
phases, each managed by a specific function:
\path{AgesaHwWlPhase1}, \path{AgesaHwWlPhase2}, and \path{AgesaHwWlPhase1}, \path{AgesaHwWlPhase2}, and
\path{AgesaHwWlPhase3} from \path{mcthwl.c}. \path{AgesaHwWlPhase3} from \path{mcthwl.c}.
These phases work together to These phases work together to