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Idt in progress !

This commit is contained in:
Adrien Bourmault 2019-04-23 17:06:03 +02:00
parent ca6c7bbcf9
commit 3dbe85b936
5 changed files with 131 additions and 73 deletions
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43
include/kernel/cpu.h
View File

@ -37,7 +37,9 @@ typedef struct IdtPtr_t IdtPtr_t;
typedef struct Registers_t Registers_t;
// -------------------------------------------------------------------------- //
//
#define interrupt(n) asm volatile ("int %0" : : "N" (n) : "cc", "memory") \
// CPU features masks
enum {
FEAT_ECX_SSE3 = 1 << 0,
@ -99,6 +101,41 @@ enum {
FEAT_EDX_PBE = 1 << 31
};
static const char *IsrExceptions[32] = {
"Divide Error Fault",
"Debug Exception Trap",
"Non-maskable Interrupt",
"Breakpoint Trap",
"Overflow Trap",
"Bound Range Exceeded Fault",
"Invalid Opcode Fault",
"Device Not Available or No Math Coprocessor Fault",
"Double Fault Abort",
"Coprocessor Segment Overrun Fault",
"Invalid TSS Fault",
"Segment Not Present Fault",
"Stack Segment fault",
"General Protection Fault",
"Page Fault",
"Reserved",
"x87 FPU Floating Point or Math Fault",
"Alignment Check Fault",
"Machine Check Abort",
"SIMD Floating Point Fault",
"Virtualization Exception Fault",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved"
};
struct IdtDescriptor_t {
ushort limit;
ulong base;
@ -134,8 +171,8 @@ struct Registers_t
// -------------------------------------------------------------------------- //
void CpuIdtSetup(void);
void idtSet(uchar rank, ulong base, ushort selector, uchar flags);
void isrHandler(Registers_t reg);
void IdtSetGate(uchar rank, ulong base, ushort selector, uchar flags);
void IdtHandler(ulong intNo);
void disablePIC(void);
// -------------------------------------------------------------------------- //

82
kaleid/kernel/cpu/idt.c
View File

@ -26,12 +26,14 @@
#include <kernel/cpu.h>
#include <kernel/boot.h>
#include <kernel/iomisc.h>
#include <extras/buf.h>
IdtEntry_t idt[256] = { 0 };
IdtPtr_t idtPtr;
void CpuIdtSetup(void)
{
// XXX detect the APIC with cpuid !
disablePIC();
ushort codeSeg = (ushort)(ulong)BtLoaderInfo.codeSegment;
@ -41,37 +43,37 @@ void CpuIdtSetup(void)
idtPtr.base = &idt;
// Set IDT gates
idtSet(0, (ulong)isr0, codeSeg, 0x8E);
idtSet(1, (ulong)isr1, codeSeg, 0x8E);
idtSet(2, (ulong)isr2, codeSeg, 0x8E);
idtSet(3, (ulong)isr3, codeSeg, 0x8E);
idtSet(4, (ulong)isr4, codeSeg, 0x8E);
idtSet(5, (ulong)isr5, codeSeg, 0x8E);
idtSet(6, (ulong)isr6, codeSeg, 0x8E);
idtSet(7, (ulong)isr7, codeSeg, 0x8E);
idtSet(8, (ulong)isr8, codeSeg, 0x8E);
idtSet(9, (ulong)isr9, codeSeg, 0x8E);
idtSet(10, (ulong)isr10, codeSeg, 0x8E);
idtSet(11, (ulong)isr11, codeSeg, 0x8E);
idtSet(12, (ulong)isr12, codeSeg, 0x8E);
idtSet(13, (ulong)isr13, codeSeg, 0x8E);
idtSet(14, (ulong)isr14, codeSeg, 0x8E);
//idtSet(15, (ulong)isr15, codeSeg, 0x8E); INTEL RESERVED
idtSet(16, (ulong)isr16, codeSeg, 0x8E);
idtSet(17, (ulong)isr17, codeSeg, 0x8E);
idtSet(18, (ulong)isr18, codeSeg, 0x8E);
idtSet(19, (ulong)isr19, codeSeg, 0x8E);
idtSet(20, (ulong)isr20, codeSeg, 0x8E);
//idtSet(21, (ulong)isr21, codeSeg, 0x8E); INTEL RESERVED
//idtSet(22, (ulong)isr22, codeSeg, 0x8E); INTEL RESERVED
//idtSet(23, (ulong)isr23, codeSeg, 0x8E); INTEL RESERVED
//idtSet(24, (ulong)isr24, codeSeg, 0x8E); INTEL RESERVED
//idtSet(25, (ulong)isr25, codeSeg, 0x8E); INTEL RESERVED
//idtSet(26, (ulong)isr26, codeSeg, 0x8E); INTEL RESERVED
//idtSet(27, (ulong)isr27, codeSeg, 0x8E); INTEL RESERVED
//idtSet(28, (ulong)isr28, codeSeg, 0x8E); INTEL RESERVED
//idtSet(29, (ulong)isr29, codeSeg, 0x8E); INTEL RESERVED
//idtSet(30, (ulong)isr30, codeSeg, 0x8E); INTEL RESERVED
IdtSetGate(0, (ulong)isr0, codeSeg, 0x8E);
IdtSetGate(1, (ulong)isr1, codeSeg, 0x8E);
IdtSetGate(2, (ulong)isr2, codeSeg, 0x8E);
IdtSetGate(3, (ulong)isr3, codeSeg, 0x8E);
IdtSetGate(4, (ulong)isr4, codeSeg, 0x8E);
IdtSetGate(5, (ulong)isr5, codeSeg, 0x8E);
IdtSetGate(6, (ulong)isr6, codeSeg, 0x8E);
IdtSetGate(7, (ulong)isr7, codeSeg, 0x8E);
IdtSetGate(8, (ulong)isr8, codeSeg, 0x8E);
IdtSetGate(9, (ulong)isr9, codeSeg, 0x8E);
IdtSetGate(10, (ulong)isr10, codeSeg, 0x8E);
IdtSetGate(11, (ulong)isr11, codeSeg, 0x8E);
IdtSetGate(12, (ulong)isr12, codeSeg, 0x8E);
IdtSetGate(13, (ulong)isr13, codeSeg, 0x8E);
IdtSetGate(14, (ulong)isr14, codeSeg, 0x8E);
IdtSetGate(15, (ulong)isr15, codeSeg, 0x8E); // INTEL RESERVED
IdtSetGate(16, (ulong)isr16, codeSeg, 0x8E);
IdtSetGate(17, (ulong)isr17, codeSeg, 0x8E);
IdtSetGate(18, (ulong)isr18, codeSeg, 0x8E);
IdtSetGate(19, (ulong)isr19, codeSeg, 0x8E);
IdtSetGate(20, (ulong)isr20, codeSeg, 0x8E);
IdtSetGate(21, (ulong)isr21, codeSeg, 0x8E); // INTEL RESERVED
IdtSetGate(22, (ulong)isr22, codeSeg, 0x8E); // INTEL RESERVED
IdtSetGate(23, (ulong)isr23, codeSeg, 0x8E); // INTEL RESERVED
IdtSetGate(24, (ulong)isr24, codeSeg, 0x8E); // INTEL RESERVED
IdtSetGate(25, (ulong)isr25, codeSeg, 0x8E); // INTEL RESERVED
IdtSetGate(26, (ulong)isr26, codeSeg, 0x8E); // INTEL RESERVED
IdtSetGate(27, (ulong)isr27, codeSeg, 0x8E); // INTEL RESERVED
IdtSetGate(28, (ulong)isr28, codeSeg, 0x8E); // INTEL RESERVED
IdtSetGate(29, (ulong)isr29, codeSeg, 0x8E); // INTEL RESERVED
IdtSetGate(30, (ulong)isr30, codeSeg, 0x8E); // INTEL RESERVED
// Load IDT
DebugLog("[IdtSetup] Filled \n");
@ -79,7 +81,7 @@ void CpuIdtSetup(void)
DebugLog("[IdtSetup] Initialized !\n");
}
void idtSet(uchar rank, ulong base, ushort selector, uchar flags)
void IdtSetGate(uchar rank, ulong base, ushort selector, uchar flags)
{
// Set Base Address
idt[rank].baseLow = base & 0xFFFF;
@ -121,8 +123,20 @@ void disablePIC(void) {
*val |= (1<<8);
}
void isrHandler(Registers_t regs)
void IdtHandler(ulong intNo)
{
DebugLog("Interrupt %d !!! \n", regs.intNo);
int irrecoverable = 0;
char *exceptionMsg = "Unhandled ISR exception";
if (intNo == 6 || intNo == 8 || intNo == 13) irrecoverable++;
if (intNo < 32) exceptionMsg = IsrExceptions[intNo];
if (irrecoverable) {
KeStartPanic("Irrecoverable exception 0x%x : %s\n", intNo, exceptionMsg);
} else {
bprintf(BStdOut, "Exception 0x%x : %s\n", intNo, exceptionMsg);
}
return;
}

21
kaleid/kernel/cpu/isr.asm
View File

@ -26,14 +26,13 @@
global idtInit
extern idtPtr
extern isrHandler
extern IdtHandler
;;
;; Loads the IDT
;;
idtInit:
lidt [idtPtr]
sti
ret
;;
@ -46,13 +45,12 @@ isrPreHandler:
mov ax, ds
push rax
call isrHandler
call IdtHandler
pop rax
mov ds, ax
popAll
add rsp, 8
sti
iretq
@ -115,3 +113,18 @@ IsrWithErrCode 13
;; Page Fault
IsrWithErrCode 14
;; Reserved
IsrWithoutErrCode 15
IsrWithoutErrCode 21
IsrWithoutErrCode 22
IsrWithoutErrCode 23
IsrWithoutErrCode 24
IsrWithoutErrCode 25
IsrWithoutErrCode 26
IsrWithoutErrCode 27
IsrWithoutErrCode 28
IsrWithoutErrCode 29
IsrWithoutErrCode 30
IsrWithoutErrCode 31
IsrWithoutErrCode 32

5
kaleid/kernel/cpu/isr.inc
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@ -45,8 +45,7 @@
global isr%1
isr%1:
cli
push byte 0
push byte %1
mov rdi, %1
jmp isrPreHandler
%endmacro
@ -54,6 +53,6 @@
global isr%1
isr%1:
cli
push byte %1
mov rdi, %1
jmp isrPreHandler
%endmacro

11
kaleid/kernel/init/init.c
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@ -40,12 +40,6 @@ extern error_t IoInitVGABuffer(void);
// ps/proc.c test function
extern void pstest(void);
void bug(void)
{
asm volatile ("int %0" : : "N" (0) : "cc", "memory");
}
//
// Entry point of the Kaleid kernel
//
@ -75,9 +69,10 @@ noreturn void BtStartKern(multiboot_info_t *mbInfo, uint mbMagic, void *codeSeg)
//MmPrintMemoryMap();
CpuIdtSetup();
KeEnableIRQs();
bug();
long a = -1;
DebugLog("%s", a);
// End this machine's suffering
BFlushBuf(BStdOut);
KeCrashSystem();