TSS works !
This commit is contained in:
Adrien Bourmault
parent
8716e896da
commit
b6e39d4712
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@ -93,3 +93,9 @@ IDT Overhaul
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2019-05-14 @os-k-team <os-k-team@os-k.eu>
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* Whole Project Tree : big reorganization
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* Makefile : dependencies automated
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2019-05-21 @os-k-team <os-k-team@os-k.eu>
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* VGA and Shell and bprintf: Color support
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* GDT : CS and TSS works
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* IDT : Double Fault and Stack Segment Fault have a separate stack
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* Stack : guard pages are now fully functionnal
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@ -41,7 +41,7 @@ struct IdtEntry_t
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{
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ushort baseLow;
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ushort selector;
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uchar reservedIst;
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uchar ist;
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uchar flags;
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ushort baseMid;
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uint baseHigh;
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@ -71,7 +71,11 @@ void KeLoadIDT(void);
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void KeSetupIDT(void);
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void KeSendEOItoPIC(uchar isr);
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void KeSetIDTGate(uchar rank, ulong base, ushort selector, uchar flags);
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void KeSetIDTGate(uchar rank,
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ulong base,
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ushort selector,
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uchar flags,
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uchar ist);
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error_t KeRegisterISR(void (*isr)(ISRFrame_t *regs), uchar isrNo);
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void KeBrkDumpRegisters(ISRFrame_t *regs);
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@ -40,6 +40,8 @@
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#define NVS_ZONE 4 // Dunno
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#define BADRAM_ZONE 5 // Invalid zone because material problem...
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#define MAX_ENTRIES 2048 // Max number of memory map entries
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#define KPAGESIZE (4 * KB)
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#define UPAGESIZE (2 * MB)
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//----------------------------------------------------------------------------//
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@ -71,15 +73,14 @@ struct GdtEntry_t
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struct TssDescriptor_t
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{
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ushort lowLimit;
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ushort lowBase;
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uchar middleBase;
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uchar access;
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unsigned middleLimit: 4;
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unsigned flags: 4;
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uchar highBase;
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uint veryHighBase;
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uint reserved;
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ushort lowLimit;
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ushort lowBase;
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uchar middleBase;
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uchar access;
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uchar flags;
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uchar highBase;
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uint veryHighBase;
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uint reserved;
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} __attribute__ ((packed));
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struct Tss_t
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@ -149,7 +150,7 @@ void MmInitGdt(void);
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//
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// Loads the descriptor table
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//
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extern void MmLoadGdt();
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extern void MmLoadGdt(GdtPtr_t *gdtPtr, ushort tssOffset);
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//
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@ -54,7 +54,6 @@ noreturn void BtStartKern(multiboot_info_t *mbInfo, uint mbMagic, void *codeSeg)
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BtDoSanityChecks(mbMagic);
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// Memory
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//MmInitGdt();
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MmInitMemoryMap();
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MmInitPaging();
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MmInitHeap();
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@ -62,6 +61,7 @@ noreturn void BtStartKern(multiboot_info_t *mbInfo, uint mbMagic, void *codeSeg)
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// Interrupts launching
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KeSetupIDT();
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KeEnableIRQs();
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MmInitGdt();
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// Start drivers
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KeEnableRTC();
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@ -31,6 +31,8 @@ IdtEntry_t idt[256] = { 0 };
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IdtPtr_t _KeIdtPtr;
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bool KeIdtIsInitialized = 0;
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extern ulong *MmStackGuards[2];
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static ISRList_t isrList = { 0 };
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static char *ExceptionsChar[32] = {
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@ -70,6 +72,10 @@ static char *ExceptionsChar[32] = {
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static void EnablePIC(void);
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static void EarlyExceptionHandler(ISRFrame_t *regs);
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static void DoubleFaultHandler(ISRFrame_t *regs);
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//paging.c
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ulong *MmGetStackGuards(void);
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//
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// Registers an isr with his IRQ to handle driver interrupts
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@ -117,56 +123,56 @@ void KeSetupIDT(void)
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_KeIdtPtr.base = &idt;
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// Set IDT Exception Gates
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KeSetIDTGate(0x00, (ulong)isr0, codeSeg, 0x8E);
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KeSetIDTGate(0x01, (ulong)isr1, codeSeg, 0x8E);
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KeSetIDTGate(0x02, (ulong)isr2, codeSeg, 0x8E);
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KeSetIDTGate(0x03, (ulong)isr3, codeSeg, 0x8E);
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KeSetIDTGate(0x04, (ulong)isr4, codeSeg, 0x8E);
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KeSetIDTGate(0x05, (ulong)isr5, codeSeg, 0x8E);
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KeSetIDTGate(0x06, (ulong)isr6, codeSeg, 0x8E);
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KeSetIDTGate(0x07, (ulong)isr7, codeSeg, 0x8E);
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KeSetIDTGate(0x08, (ulong)isr8, codeSeg, 0x8E);
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KeSetIDTGate(0x09, (ulong)isr9, codeSeg, 0x8E);
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KeSetIDTGate(0x0A, (ulong)isr10, codeSeg, 0x8E);
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KeSetIDTGate(0x0B, (ulong)isr11, codeSeg, 0x8E);
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KeSetIDTGate(0x0C, (ulong)isr12, codeSeg, 0x8E);
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KeSetIDTGate(0x0D, (ulong)isr13, codeSeg, 0x8E);
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KeSetIDTGate(0x0E, (ulong)isr14, codeSeg, 0x8E);
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KeSetIDTGate(0x0F, (ulong)isr15, codeSeg, 0x8E); // INTEL RESERVED
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KeSetIDTGate(0x10, (ulong)isr16, codeSeg, 0x8E);
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KeSetIDTGate(0x11, (ulong)isr17, codeSeg, 0x8E);
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KeSetIDTGate(0x12, (ulong)isr18, codeSeg, 0x8E);
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KeSetIDTGate(0x13, (ulong)isr19, codeSeg, 0x8E);
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KeSetIDTGate(0x14, (ulong)isr20, codeSeg, 0x8E);
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KeSetIDTGate(0x15, (ulong)isr21, codeSeg, 0x8E); // INTEL RESERVED
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KeSetIDTGate(0x16, (ulong)isr22, codeSeg, 0x8E); // INTEL RESERVED
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KeSetIDTGate(0x17, (ulong)isr23, codeSeg, 0x8E); // INTEL RESERVED
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KeSetIDTGate(0x18, (ulong)isr24, codeSeg, 0x8E); // INTEL RESERVED
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KeSetIDTGate(0x19, (ulong)isr25, codeSeg, 0x8E); // INTEL RESERVED
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KeSetIDTGate(0x1A, (ulong)isr26, codeSeg, 0x8E); // INTEL RESERVED
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KeSetIDTGate(0x1B, (ulong)isr27, codeSeg, 0x8E); // INTEL RESERVED
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KeSetIDTGate(0x1C, (ulong)isr28, codeSeg, 0x8E); // INTEL RESERVED
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KeSetIDTGate(0x1D, (ulong)isr29, codeSeg, 0x8E); // INTEL RESERVED
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KeSetIDTGate(0x1E, (ulong)isr30, codeSeg, 0x8E);
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KeSetIDTGate(0x1F, (ulong)isr31, codeSeg, 0x8E); // INTEL RESERVED
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KeSetIDTGate(0x00, (ulong)isr0, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x01, (ulong)isr1, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x02, (ulong)isr2, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x03, (ulong)isr3, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x04, (ulong)isr4, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x05, (ulong)isr5, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x06, (ulong)isr6, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x07, (ulong)isr7, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x08, (ulong)isr8, codeSeg, 0x8E, 1);
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KeSetIDTGate(0x09, (ulong)isr9, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x0A, (ulong)isr10, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x0B, (ulong)isr11, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x0C, (ulong)isr12, codeSeg, 0x8E, 1);
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KeSetIDTGate(0x0D, (ulong)isr13, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x0E, (ulong)isr14, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x0F, (ulong)isr15, codeSeg, 0x8E, 0); // INTEL RESERVED
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KeSetIDTGate(0x10, (ulong)isr16, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x11, (ulong)isr17, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x12, (ulong)isr18, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x13, (ulong)isr19, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x14, (ulong)isr20, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x15, (ulong)isr21, codeSeg, 0x8E, 0); // INTEL RESERVED
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KeSetIDTGate(0x16, (ulong)isr22, codeSeg, 0x8E, 0); // INTEL RESERVED
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KeSetIDTGate(0x17, (ulong)isr23, codeSeg, 0x8E, 0); // INTEL RESERVED
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KeSetIDTGate(0x18, (ulong)isr24, codeSeg, 0x8E, 0); // INTEL RESERVED
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KeSetIDTGate(0x19, (ulong)isr25, codeSeg, 0x8E, 0); // INTEL RESERVED
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KeSetIDTGate(0x1A, (ulong)isr26, codeSeg, 0x8E, 0); // INTEL RESERVED
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KeSetIDTGate(0x1B, (ulong)isr27, codeSeg, 0x8E, 0); // INTEL RESERVED
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KeSetIDTGate(0x1C, (ulong)isr28, codeSeg, 0x8E, 0); // INTEL RESERVED
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KeSetIDTGate(0x1D, (ulong)isr29, codeSeg, 0x8E, 0); // INTEL RESERVED
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KeSetIDTGate(0x1E, (ulong)isr30, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x1F, (ulong)isr31, codeSeg, 0x8E, 0); // INTEL RESERVED
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// Set IDT IRQs Gates
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KeSetIDTGate(0x20, (ulong)isr32, codeSeg, 0x8E);
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KeSetIDTGate(0x21, (ulong)isr33, codeSeg, 0x8E);
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KeSetIDTGate(0x22, (ulong)isr34, codeSeg, 0x8E);
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KeSetIDTGate(0x23, (ulong)isr35, codeSeg, 0x8E);
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KeSetIDTGate(0x24, (ulong)isr36, codeSeg, 0x8E);
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KeSetIDTGate(0x25, (ulong)isr37, codeSeg, 0x8E);
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KeSetIDTGate(0x26, (ulong)isr38, codeSeg, 0x8E);
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KeSetIDTGate(0x27, (ulong)isr39, codeSeg, 0x8E);
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KeSetIDTGate(0x28, (ulong)isr40, codeSeg, 0x8E);
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KeSetIDTGate(0x29, (ulong)isr41, codeSeg, 0x8E);
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KeSetIDTGate(0x2A, (ulong)isr42, codeSeg, 0x8E);
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KeSetIDTGate(0x2B, (ulong)isr43, codeSeg, 0x8E);
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KeSetIDTGate(0x2C, (ulong)isr44, codeSeg, 0x8E);
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KeSetIDTGate(0x2D, (ulong)isr45, codeSeg, 0x8E);
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KeSetIDTGate(0x2E, (ulong)isr46, codeSeg, 0x8E);
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KeSetIDTGate(0x2F, (ulong)isr47, codeSeg, 0x8E);
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KeSetIDTGate(0x20, (ulong)isr32, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x21, (ulong)isr33, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x22, (ulong)isr34, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x23, (ulong)isr35, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x24, (ulong)isr36, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x25, (ulong)isr37, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x26, (ulong)isr38, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x27, (ulong)isr39, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x28, (ulong)isr40, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x29, (ulong)isr41, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x2A, (ulong)isr42, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x2B, (ulong)isr43, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x2C, (ulong)isr44, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x2D, (ulong)isr45, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x2E, (ulong)isr46, codeSeg, 0x8E, 0);
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KeSetIDTGate(0x2F, (ulong)isr47, codeSeg, 0x8E, 0);
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KeIdtIsInitialized++;
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@ -176,6 +182,7 @@ void KeSetupIDT(void)
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}
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KeRegisterISR(KeBrkDumpRegisters, 0x3);
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KeRegisterISR(DoubleFaultHandler, 0x8);
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// Load IDT
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KeLoadIDT();
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@ -185,7 +192,7 @@ void KeSetupIDT(void)
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//
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// Set an interrupt gate
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//
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void KeSetIDTGate(uchar rank, ulong base, ushort selector, uchar flags)
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void KeSetIDTGate(uchar rank, ulong base, ushort selector, uchar flags, uchar ist)
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{
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// Set Base Address
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idt[rank].baseLow = base & 0xFFFF;
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@ -197,7 +204,7 @@ void KeSetIDTGate(uchar rank, ulong base, ushort selector, uchar flags)
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idt[rank].flags = flags;
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// Set Reserved Areas to Zero
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idt[rank].reservedIst = 0;
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idt[rank].ist = ist;
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idt[rank].reserved = 0;
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}
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@ -296,6 +303,40 @@ static void EarlyExceptionHandler(ISRFrame_t *regs)
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KeHaltCPU();
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}
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static void DoubleFaultHandler(ISRFrame_t *regs)
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{
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bprintf(BStdOut, "test : %p\n", (ulong)(MmGetStackGuards())[0] + 4*KB);
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if (regs->rsp <= (ulong)(MmGetStackGuards())[0] + 4*KB) {
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bprintf(BStdOut,
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"\n\n%CPANIC\n[ISR 0x8] Irrecoverable Kernel Stack Overflow%s\n\n"
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" Error code : 0x%x (%b)",
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VGA_COLOR_LIGHT_RED,
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regs->intNo,
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ExceptionsChar[regs->intNo],
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regs->ErrorCode,
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regs->ErrorCode
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);
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} else {
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bprintf(BStdOut,
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"\n\n%CPANIC\n[ISR 0x8] Irrecoverable Kernel Double Fault Abort\n\n"
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" Error code : 0x%x (%b)",
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VGA_COLOR_LIGHT_RED,
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regs->ErrorCode,
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regs->ErrorCode
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);
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}
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KeBrkDumpRegisters(regs);
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BStdOut->flusher(BStdOut);
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KeHaltCPU();
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}
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void KeBrkDumpRegisters(ISRFrame_t *regs)
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{
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bprintf(BStdOut, "\n\n"
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@ -24,8 +24,6 @@
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[BITS 64]
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extern gdtPtr
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global MmLoadGdt
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global MmStoreGdt
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@ -34,7 +32,9 @@ global MmStoreGdt
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;;
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MmLoadGdt:
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;; Loading the gdt via the gdtPtr pointer
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lgdt [gdtPtr]
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lgdt [rdi]
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mov ax, si
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ltr ax
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;; We must far jump because we changed the GDT
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lea rax, [.next]
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@ -49,5 +49,5 @@ MmLoadGdt:
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;;
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MmStoreGdt:
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;; Loading the gdt via the gdtPtr pointer
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sgdt [gdtPtr]
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sgdt [rdi]
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ret
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@ -23,89 +23,67 @@
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//----------------------------------------------------------------------------//
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#include <mm/mm.h>
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#include <init/boot.h>
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//Tss_t tssEntry = { 0 };
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GdtPtr_t gdtPtr;
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/* static void SetGdtEntry(int index, uint base, uint limit, uchar access) */
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/* { */
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/* gdtEntries[index].lowBase = (base & 0xFFFF); */
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/* gdtEntries[index].middleBase = (base >> 16) & 0xFF; */
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/* gdtEntries[index].highBase = (base >> 24) & 0xFF; */
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/* gdtEntries[index].lowLimit = (limit & 0xFFFF); */
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/* gdtEntries[index].granularity = (limit >> 16) & 0x0F; */
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/* gdtEntries[index].granularity |= 0xA0; */
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/* // 0x10 is system */
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/* // 0x80 is present */
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/* gdtEntries[index].access = access | 0x10 | 0x80; */
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/* } */
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/* static void SetTssEntry(uchar index, ulong base, ulong limit) */
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/* { */
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/* TssDescriptor_t tssDesc = { 0 }; */
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/* tssDesc.limitLow = limit & 0xffff; */
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/* tssDesc.size = (limit >> 16) & 0xf; */
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/* tssDesc.base00 = base & 0xffff; */
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/* tssDesc.base16 = (base >> 16) & 0xff; */
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/* tssDesc.base24 = (base >> 24) & 0xff; */
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/* tssDesc.base32 = (base >> 32) & 0xffffffff; */
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/* tssDesc.reserved = 0; */
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/* tssDesc.access = 0x01 | 0x08 | 0x10 | 0x80; */
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/* memmove(&gdtEntries[index], &tssDesc, sizeof(TssDescriptor_t)); */
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/* } */
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GdtEntry_t gdt[4] __attribute__((__aligned__(KPAGESIZE)));
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TssDescriptor_t tssDesc __attribute__((__aligned__(KPAGESIZE)));
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Tss_t tss __attribute__((__aligned__(KPAGESIZE)));
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void MmInitGdt(void)
|
||||
{
|
||||
MmStoreGdt();
|
||||
ushort tssOffset = (ushort)((ulong)(&gdt[2]) - (ulong)(&gdt[0]));
|
||||
|
||||
GdtEntry_t *gdt = (GdtEntry_t *)(gdtPtr.base);
|
||||
extern ulong GDT64;
|
||||
gdtPtr.base = (ulong)&gdt[0];
|
||||
gdtPtr.limit = sizeof(gdt) - 1;
|
||||
|
||||
DebugLog("GDT ADDR: %p\n",
|
||||
gdt
|
||||
);
|
||||
memzero((void *)&gdt[0], sizeof(gdt));
|
||||
memzero((void *)&tssDesc, sizeof(tssDesc));
|
||||
memzero((void *)&tss, sizeof(tss));
|
||||
|
||||
gdt++;
|
||||
gdt[1].lowLimit = 0xFFFF;
|
||||
gdt[1].access = 0x98;
|
||||
gdt[1].flags = 0x20;
|
||||
|
||||
DebugLog("GDT : \n"
|
||||
"lowLimit : %#016hx\n"
|
||||
"lowBase : %#016hx\n"
|
||||
"middleBase: %#016hx\n"
|
||||
"access : %#016hx\n"
|
||||
"flags : %#016hx\n"
|
||||
"highBase : %#016hx\n",
|
||||
gdt->lowLimit,
|
||||
gdt->lowBase,
|
||||
gdt->middleBase,
|
||||
gdt->access,
|
||||
gdt->flags,
|
||||
gdt->highBase
|
||||
);
|
||||
tssDesc.access = 0x89;
|
||||
tssDesc.flags = 0x40;
|
||||
tssDesc.lowBase = (ulong)&tss & 0xFFFF;
|
||||
tssDesc.middleBase = ((ulong)&tss >> 16) & 0xFF;
|
||||
tssDesc.highBase = ((ulong)&tss >> 24) & 0xFF;
|
||||
tssDesc.veryHighBase = ((ulong)&tss >> 32) & 0xFFFFFFFF;
|
||||
tssDesc.lowLimit = sizeof(tss);
|
||||
|
||||
/* DebugLog("GDT : \n" */
|
||||
/* "lowLimit : %#016hx\n" */
|
||||
/* "lowBase : %#016hx\n" */
|
||||
/* "middleBase: %#016hx\n" */
|
||||
/* "access : %#016hx\n" */
|
||||
/* "flags : %#016hx\n" */
|
||||
/* "highBase : %#016hx\n", */
|
||||
/* gdt->lowLimit, */
|
||||
/* gdt->lowBase, */
|
||||
/* gdt->middleBase, */
|
||||
/* gdt->access, */
|
||||
/* gdt->flags, */
|
||||
/* gdt->highBase */
|
||||
/* ); */
|
||||
tss.ist1 = 0x0007FFFF; // RESCUE STACK, GARANTIED FREE FOR USE BY OSDEV.ORG
|
||||
tss.iomap_base = sizeof(tss);
|
||||
|
||||
MmLoadGdt();
|
||||
memmove(&gdt[2], &tssDesc, sizeof(TssDescriptor_t));
|
||||
|
||||
/* DebugLog("TSS\n" */
|
||||
/* "gdt[0] %#x\n" */
|
||||
/* "gdt[2] %#x\n" */
|
||||
/* "access : %#x\n" */
|
||||
/* "flags : %#x\n" */
|
||||
/* "lowBase : %#x\n" */
|
||||
/* "middleBase : %#x\n" */
|
||||
/* "highBase : %#x\n" */
|
||||
/* "veryHighBase: %#x\n" */
|
||||
/* "lowLimit : %#x\n" */
|
||||
/* "ist : %#x\n" */
|
||||
/* "iomap_base : %#x\n" */
|
||||
/* "offset : %#x\n", */
|
||||
/* &gdt[0], */
|
||||
/* &gdt[2], */
|
||||
/* tssDesc.access, */
|
||||
/* tssDesc.flags, */
|
||||
/* tssDesc.lowBase, */
|
||||
/* tssDesc.middleBase, */
|
||||
/* tssDesc.highBase, */
|
||||
/* tssDesc.veryHighBase, */
|
||||
/* tssDesc.lowLimit, */
|
||||
/* tss.ist1, */
|
||||
/* tss.iomap_base, */
|
||||
/* tssOffset */
|
||||
/* ); */
|
||||
|
||||
MmLoadGdt(&gdtPtr, tssOffset);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -7,10 +7,6 @@
|
|||
#include <io/vga.h>
|
||||
|
||||
|
||||
#define KPAGESIZE (4 * KB)
|
||||
#define UPAGESIZE (2 * MB)
|
||||
|
||||
|
||||
// Page directory pointer offset
|
||||
typedef ulong pdpe_t;
|
||||
|
||||
|
|
@ -52,7 +48,7 @@ volatile pde_t MmPD[512 * RAM_MAX] __attribute__((__aligned__(KPAGESIZE)));;
|
|||
|
||||
volatile pte_t MmPT[512 * NB_4K] __attribute__((__aligned__(KPAGESIZE)));;
|
||||
|
||||
volatile ulong MmStackGuards[2] = { 0 };
|
||||
ulong MmStackGuards[2] = { 0 };
|
||||
|
||||
//
|
||||
// Creates our new page table structure and loads it
|
||||
|
|
@ -112,6 +108,7 @@ void MmInitPaging(void)
|
|||
|
||||
MmLoadPML4((void *)MmPML4);
|
||||
DebugLog("\tPaging tables initialized at %p, %p\n", &MmPD, &MmPT);
|
||||
DebugLog("\tStack Guards at %p, %p\n", MmStackGuards[0], MmStackGuards[1]);
|
||||
}
|
||||
|
||||
//
|
||||
|
|
@ -160,6 +157,7 @@ void MmReloadPaging(void)
|
|||
}
|
||||
|
||||
DebugLog("Paging tables reloaded at %p, %p\n", &MmPD, &MmPT);
|
||||
DebugLog("Stack Guards at %p, %p\n", MmStackGuards[0], MmStackGuards[1]);
|
||||
}
|
||||
|
||||
//
|
||||
|
|
@ -188,3 +186,8 @@ void MmActivatePageHandler(void)
|
|||
{
|
||||
KeRegisterISR(PagingHandler, 0xe);
|
||||
}
|
||||
|
||||
ulong *MmGetStackGuards(void)
|
||||
{
|
||||
return &MmStackGuards[0];
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue