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coreboot-kgpe-d16/src/soc/intel/apollolake/pmc.c

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soc/apollolake: Prevent PMC BAR reassignment during resource allocation Change-Id: Ie8e21e62ecd25f3c620a57c24948411c14c1e111 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14315 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11 22:46:28 +01:00
/*
* This file is part of the coreboot project.
*
soc/intel/common/block: Add Intel common PMC controller support for KBL, APL SoC needs to select specific macros to compile commom PMC code. TEST=Build and boot KBL (soraka/eve), APL (reef) Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-22 11:08:19 +01:00
* Copyright (C) 2016-2017 Intel Corp.
soc/apollolake: Handle non-standard ACPI BAR in PMC device The ACPI BAR (BAR2 - offset 0x20) is not PCI compliant. That means that probing may not work. In that case, a resource still needs to be created for the BAR. BONUS: We now avoid the need to declare the MMIO resources as fixed. Change-Id: I52fd2d2718ac8013067aaa450c5eb31e00738ab9 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14634 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-06 19:49:55 +02:00
* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
soc/apollolake: Prevent PMC BAR reassignment during resource allocation Change-Id: Ie8e21e62ecd25f3c620a57c24948411c14c1e111 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14315 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11 22:46:28 +01:00
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
soc/intel/common/block: Add Intel common PMC controller support for KBL, APL SoC needs to select specific macros to compile commom PMC code. TEST=Build and boot KBL (soraka/eve), APL (reef) Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-22 11:08:19 +01:00
#include "chip.h"
#include <console/console.h>
device/mmio.h: Add include file for MMIO ops MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-03 07:01:05 +01:00
#include <device/mmio.h>
soc/apollolake: Prevent PMC BAR reassignment during resource allocation Change-Id: Ie8e21e62ecd25f3c620a57c24948411c14c1e111 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14315 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11 22:46:28 +01:00
#include <device/device.h>
#include <device/pci.h>
soc/intel/common/block: Add Intel common PMC controller support for KBL, APL SoC needs to select specific macros to compile commom PMC code. TEST=Build and boot KBL (soraka/eve), APL (reef) Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-22 11:08:19 +01:00
#include <intelblocks/pmc.h>
soc/intel/apollolake: Use common PMC for apollolake With this patch apollolake uses the common PMC util code.No regression observed on a APL platform. Change-Id: I322a25a8b608d7fe98bec626c6696e723357a9d2 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/19375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19 00:42:09 +02:00
#include <intelblocks/pmclib.h>
soc/apollolake: Prevent PMC BAR reassignment during resource allocation Change-Id: Ie8e21e62ecd25f3c620a57c24948411c14c1e111 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14315 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11 22:46:28 +01:00
#include <soc/iomap.h>
soc/intel/apollolake: Add GPE routing code This patch adds the basic framework for SCI to GPE routing code. BUG = chrome-os-partner:53438 TEST = Toogle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupts. Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15324 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-07 11:06:28 +02:00
#include <soc/pm.h>
soc/intel/apollolake: add option for SLP_S3_L assertion width In order to provide time for the S0 rails to discharge one needs to be able to set the SLP_S3_L assertion width. The hardware default is 60 microcseconds which is not slow enough on most boards. Therefore provide a devicetree option for the mainboard to set accordingly for its needs. An unset value in devicetree results in a conservative 2 second SLP_S3_L duration. BUG=chrome-os-partner:56581 Change-Id: I6c6df2f7a181746708ab7897249ae82109c55f50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16326 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-08-25 22:42:04 +02:00
#include <timer.h>
soc/apollolake: Prevent PMC BAR reassignment during resource allocation Change-Id: Ie8e21e62ecd25f3c620a57c24948411c14c1e111 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14315 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11 22:46:28 +01:00
soc/intel/common/block: Add Intel common PMC controller support for KBL, APL SoC needs to select specific macros to compile commom PMC code. TEST=Build and boot KBL (soraka/eve), APL (reef) Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-22 11:08:19 +01:00
/* Fill up PMC resource structure */
int pmc_soc_get_resources(struct pmc_resource_config *cfg)
soc/apollolake: Prevent PMC BAR reassignment during resource allocation Change-Id: Ie8e21e62ecd25f3c620a57c24948411c14c1e111 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14315 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11 22:46:28 +01:00
{
soc/intel/common/block: Add Intel common PMC controller support for KBL, APL SoC needs to select specific macros to compile commom PMC code. TEST=Build and boot KBL (soraka/eve), APL (reef) Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-22 11:08:19 +01:00
cfg->pwrmbase_offset = PCI_BASE_ADDRESS_0;
cfg->pwrmbase_addr = PMC_BAR0;
cfg->pwrmbase_size = PMC_BAR0_SIZE;
cfg->abase_offset = PCI_BASE_ADDRESS_4;
cfg->abase_addr = ACPI_BASE_ADDRESS;
cfg->abase_size = ACPI_BASE_SIZE;
return 0;
soc/apollolake: add GPIO SMI support GPIOs which trigger SMIs set the GPIO_SMI_STS status bits in SMI_STS register. This patch also sets the SMI_EN bit in enable register for each community based on GPIOROUTSMI bit in gpio pad. When SMI on a gpio happens status needs to be gathered on gpio number which is done by reading the GPI_SMI_STS and GPI_SMI_EN registers. BUG=chrome-os-partner:54977 TEST=When system is in firmware mode executing the command lidclose from ec console shuts down the system. Change-Id: Id89a526106d1989c2bd3416ab81913e6cf743d17 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15833 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-25 05:50:12 +02:00
}
soc/intel/apollolake: add option for SLP_S3_L assertion width In order to provide time for the S0 rails to discharge one needs to be able to set the SLP_S3_L assertion width. The hardware default is 60 microcseconds which is not slow enough on most boards. Therefore provide a devicetree option for the mainboard to set accordingly for its needs. An unset value in devicetree results in a conservative 2 second SLP_S3_L duration. BUG=chrome-os-partner:56581 Change-Id: I6c6df2f7a181746708ab7897249ae82109c55f50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16326 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-08-25 22:42:04 +02:00
static int choose_slp_s3_assertion_width(int width_usecs)
{
int i;
static const struct {
int max_width;
int value;
} slp_s3_settings[] = {
{
.max_width = 60,
.value = SLP_S3_ASSERT_60_USEC,
},
{
.max_width = 1 * USECS_PER_MSEC,
.value = SLP_S3_ASSERT_1_MSEC,
},
{
.max_width = 50 * USECS_PER_MSEC,
.value = SLP_S3_ASSERT_50_MSEC,
},
{
.max_width = 2 * USECS_PER_SEC,
.value = SLP_S3_ASSERT_2_SEC,
},
};
for (i = 0; i < ARRAY_SIZE(slp_s3_settings); i++) {
if (width_usecs <= slp_s3_settings[i].max_width)
break;
}
/* Provide conservative default if nothing set in devicetree
* or requested assertion width too large. */
if (width_usecs <= 0 || i == ARRAY_SIZE(slp_s3_settings))
i = ARRAY_SIZE(slp_s3_settings) - 1;
printk(BIOS_DEBUG, "SLP S3 assertion width: %d usecs\n",
slp_s3_settings[i].max_width);
return slp_s3_settings[i].value;
}
static void set_slp_s3_assertion_width(int width_usecs)
{
uint32_t reg;
soc/intel/apollolake: Use common PMC for apollolake With this patch apollolake uses the common PMC util code.No regression observed on a APL platform. Change-Id: I322a25a8b608d7fe98bec626c6696e723357a9d2 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/19375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19 00:42:09 +02:00
uintptr_t gen_pmcon3 = soc_read_pmc_base() + GEN_PMCON3;
soc/intel/apollolake: add option for SLP_S3_L assertion width In order to provide time for the S0 rails to discharge one needs to be able to set the SLP_S3_L assertion width. The hardware default is 60 microcseconds which is not slow enough on most boards. Therefore provide a devicetree option for the mainboard to set accordingly for its needs. An unset value in devicetree results in a conservative 2 second SLP_S3_L duration. BUG=chrome-os-partner:56581 Change-Id: I6c6df2f7a181746708ab7897249ae82109c55f50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16326 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-08-25 22:42:04 +02:00
int setting = choose_slp_s3_assertion_width(width_usecs);
reg = read32((void *)gen_pmcon3);
reg &= ~SLP_S3_ASSERT_MASK;
reg |= setting << SLP_S3_ASSERT_WIDTH_SHIFT;
write32((void *)gen_pmcon3, reg);
}
soc/intel/common/block: Add Intel common PMC controller support for KBL, APL SoC needs to select specific macros to compile commom PMC code. TEST=Build and boot KBL (soraka/eve), APL (reef) Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-22 11:08:19 +01:00
void pmc_soc_init(struct device *dev)
soc/intel/apollolake: Add GPE routing code This patch adds the basic framework for SCI to GPE routing code. BUG = chrome-os-partner:53438 TEST = Toogle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupts. Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15324 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-07 11:06:28 +02:00
{
soc/intel: Use config_of() Change-Id: I0727a6b327410197cf32f598d1312737744386b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian
2019-07-13 21:16:25 +02:00
const struct soc_intel_apollolake_config *cfg = config_of(dev);
soc/intel/apollolake: add option for SLP_S3_L assertion width In order to provide time for the S0 rails to discharge one needs to be able to set the SLP_S3_L assertion width. The hardware default is 60 microcseconds which is not slow enough on most boards. Therefore provide a devicetree option for the mainboard to set accordingly for its needs. An unset value in devicetree results in a conservative 2 second SLP_S3_L duration. BUG=chrome-os-partner:56581 Change-Id: I6c6df2f7a181746708ab7897249ae82109c55f50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16326 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-08-25 22:42:04 +02:00
soc/intel/apollolake: Add GPE routing code This patch adds the basic framework for SCI to GPE routing code. BUG = chrome-os-partner:53438 TEST = Toogle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupts. Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15324 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-07 11:06:28 +02:00
/* Set up GPE configuration */
pmc_gpe_init();
soc/intel/common/block: Add Intel common PMC controller support for KBL, APL SoC needs to select specific macros to compile commom PMC code. TEST=Build and boot KBL (soraka/eve), APL (reef) Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-22 11:08:19 +01:00
pmc_set_acpi_mode();
soc/intel/apollolake: Enable ELOG Add in the base for ELOG for APL. Some PM events still need to be added but the basic events are logged here. This enables the basic functionality of ELOG for Apollolake. BUG=chrome-os-partner:55473 BRANCH=none TEST=Verified image boots on Amenia Change-Id: I8682293e5a55b3efb5fdd9f1be1f3e4bf8d0757c Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/15937 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-19 00:14:12 +02:00
soc/intel/apollolake: add option for SLP_S3_L assertion width In order to provide time for the S0 rails to discharge one needs to be able to set the SLP_S3_L assertion width. The hardware default is 60 microcseconds which is not slow enough on most boards. Therefore provide a devicetree option for the mainboard to set accordingly for its needs. An unset value in devicetree results in a conservative 2 second SLP_S3_L duration. BUG=chrome-os-partner:56581 Change-Id: I6c6df2f7a181746708ab7897249ae82109c55f50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16326 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-08-25 22:42:04 +02:00
if (cfg != NULL)
set_slp_s3_assertion_width(cfg->slp_s3_assertion_width_usecs);
soc/intel/apollolake: Enable ELOG Add in the base for ELOG for APL. Some PM events still need to be added but the basic events are logged here. This enables the basic functionality of ELOG for Apollolake. BUG=chrome-os-partner:55473 BRANCH=none TEST=Verified image boots on Amenia Change-Id: I8682293e5a55b3efb5fdd9f1be1f3e4bf8d0757c Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/15937 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-19 00:14:12 +02:00
/* Log power state */
pch_log_state();
soc/intel/apollolake: clear PMC registers The clearing of the PMC registers was not being called resulting in state persisting across reboots. This state is queried and events are added to the eventlog like 'RTC reset' events. However, the RTC reset event is a one time thing so it should only be logged once. Without the clearing of the state the event was logged on every boot. BUG=chrome-os-partner:58496 Change-Id: I60aa7102977c2b1775ab8c54d1c147737d2af5e2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17027 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-14 17:44:23 +02:00
/* Now that things have been logged clear out the PMC state. */
soc/intel/common: Clean up PMC library GPE handling API 1. Update gpe handling function names to explicitly mention if they are operating on: a. STD GPE events b. GPIO GPE events c. Both 2. Update comment block in pmclib.h to use generic names for STD and GPIO GPE registers instead of using any one platform specific names. BUG=b:67712608 Change-Id: I03349fe85ac31d4215418b884afd8c4b531e68d3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21968 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 23:44:29 +02:00
pmc_clear_prsts();
soc/intel/apollolake: Add GPE routing code This patch adds the basic framework for SCI to GPE routing code. BUG = chrome-os-partner:53438 TEST = Toogle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupts. Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15324 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-07 11:06:28 +02:00
}
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