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coreboot-kgpe-d16/src/soc/intel/alderlake/chipset.cb

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soc/intel/alderlake: Add initial chipset.cb Similar to the chipset.cb for TGL, this patch gives alias names to all of the published PCI devices. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6576ef4237c1fc8439795ad5b64b1840504edf73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48009 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24 21:48:56 +01:00
chip soc/intel/alderlake
device domain 0 on
soc/intel: hook up new gpio device in the soc chips This change adds the required gpio operations struct to soc/common gpio code and hooks them up in all socs currently using the gpio block code, except DNV-NS, which is handled in a separate change. Also, add the gpio device to existing chipset devicetrees. Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with CB:48711 and OCP DeltaLake with CB:48672. Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48583 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11 22:13:44 +01:00
device gpio 0 alias pch_gpio on end
soc/intel/alderlake: Add initial chipset.cb Similar to the chipset.cb for TGL, this patch gives alias names to all of the published PCI devices. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6576ef4237c1fc8439795ad5b64b1840504edf73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48009 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24 21:48:56 +01:00
device pci 00.0 alias system_agent on end
device pci 01.0 alias pcie5 off end
device pci 02.0 alias igpu off end
device pci 04.0 alias dtt off end
soc/intel/adl, mb/google/brya: Add IPU to devicetree BUG=b:181843816 Change-Id: I25309a8f0900070a8307fbce90ccb6d47f9c3dfc Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51261 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-04 18:56:28 +01:00
device pci 05.0 alias ipu off end
soc/intel/alderlake: Add initial chipset.cb Similar to the chipset.cb for TGL, this patch gives alias names to all of the published PCI devices. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6576ef4237c1fc8439795ad5b64b1840504edf73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48009 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24 21:48:56 +01:00
device pci 06.0 alias pcie4_0 off end
device pci 06.2 alias pcie4_1 off end
soc/intel/alderlake: Update chipset.cb for TCSS and USB Follow TGL chipset.cb to add alias for TCSS and USB ports. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I803dad0af09b26a55ffb767826ba79cf61de04ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/48793 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21 09:57:49 +01:00
device pci 07.0 alias tbt_pcie_rp0 off
chip soc/intel/common/block/usb4
use tcss_dma0 as usb4_port
device generic 0 on end
end
end
device pci 07.1 alias tbt_pcie_rp1 off
chip soc/intel/common/block/usb4
use tcss_dma0 as usb4_port
device generic 1 on end
end
end
device pci 07.2 alias tbt_pcie_rp2 off
chip soc/intel/common/block/usb4
use tcss_dma1 as usb4_port
device generic 0 on end
end
end
device pci 07.3 alias tbt_pcie_rp3 off
chip soc/intel/common/block/usb4
use tcss_dma1 as usb4_port
device generic 1 on end
end
end
soc/intel/alderlake: Add initial chipset.cb Similar to the chipset.cb for TGL, this patch gives alias names to all of the published PCI devices. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6576ef4237c1fc8439795ad5b64b1840504edf73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48009 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24 21:48:56 +01:00
device pci 08.0 alias gna off end
device pci 09.0 alias north_tracehub off end
soc/intel/alderlake: Add CrashLog implementation for Intel ADL This enables CrashLog for Intel ADL based platform. BUG=b:183981959 TEST=CrashLog data generated, extracted, processed and decoded sucessfully on adl-m RVP. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: I15ba0b41f73c1772f09584f13bcf5585caa90782 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52454 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-17 06:20:39 +02:00
device pci 0a.0 alias crashlog on end
soc/intel/alderlake: Update chipset.cb for TCSS and USB Follow TGL chipset.cb to add alias for TCSS and USB ports. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I803dad0af09b26a55ffb767826ba79cf61de04ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/48793 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21 09:57:49 +01:00
device pci 0d.0 alias tcss_xhci off
chip drivers/usb/acpi
register "type" = "UPC_TYPE_HUB"
device usb 0.0 alias tcss_root_hub off
chip drivers/usb/acpi
device usb 3.0 alias tcss_usb3_port1 off end
end
chip drivers/usb/acpi
device usb 3.1 alias tcss_usb3_port2 off end
end
chip drivers/usb/acpi
device usb 3.2 alias tcss_usb3_port3 off end
end
chip drivers/usb/acpi
device usb 3.3 alias tcss_usb3_port4 off end
end
end
end
end
soc/intel/alderlake: Align chipset.cb with pci_devs.h Refer pci_devs.h naming to align chipset.cb. Correct thc0, thc1 and add cnvi_bt. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Iac33983dc12ed4e5b9257c50d82adc8e4e728ad6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48153 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 14:20:13 +01:00
device pci 0d.1 alias tcss_xdci off end
device pci 0d.2 alias tcss_dma0 off end
device pci 0d.3 alias tcss_dma1 off end
soc/intel/alderlake: Add initial chipset.cb Similar to the chipset.cb for TGL, this patch gives alias names to all of the published PCI devices. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6576ef4237c1fc8439795ad5b64b1840504edf73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48009 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24 21:48:56 +01:00
device pci 0e.0 alias vmd off end
soc/intel/alderlake: Align chipset.cb with pci_devs.h Refer pci_devs.h naming to align chipset.cb. Correct thc0, thc1 and add cnvi_bt. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Iac33983dc12ed4e5b9257c50d82adc8e4e728ad6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48153 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 14:20:13 +01:00
device pci 10.0 alias thc0 off end
device pci 10.1 alias thc1 off end
soc/intel/alderlake: Add initial chipset.cb Similar to the chipset.cb for TGL, this patch gives alias names to all of the published PCI devices. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6576ef4237c1fc8439795ad5b64b1840504edf73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48009 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24 21:48:56 +01:00
device pci 12.0 alias ish off end
device pci 12.6 alias gspi2 off end
device pci 13.0 alias gspi3 off end
soc/intel/alderlake: Update chipset.cb for TCSS and USB Follow TGL chipset.cb to add alias for TCSS and USB ports. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I803dad0af09b26a55ffb767826ba79cf61de04ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/48793 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21 09:57:49 +01:00
device pci 14.0 alias xhci off
chip drivers/usb/acpi
register "type" = "UPC_TYPE_HUB"
device usb 0.0 alias xhci_root_hub off
chip drivers/usb/acpi
device usb 2.0 alias usb2_port1 off end
end
chip drivers/usb/acpi
device usb 2.1 alias usb2_port2 off end
end
chip drivers/usb/acpi
device usb 2.2 alias usb2_port3 off end
end
chip drivers/usb/acpi
device usb 2.3 alias usb2_port4 off end
end
chip drivers/usb/acpi
device usb 2.4 alias usb2_port5 off end
end
chip drivers/usb/acpi
device usb 2.5 alias usb2_port6 off end
end
chip drivers/usb/acpi
device usb 2.6 alias usb2_port7 off end
end
chip drivers/usb/acpi
device usb 2.7 alias usb2_port8 off end
end
chip drivers/usb/acpi
device usb 2.8 alias usb2_port9 off end
end
chip drivers/usb/acpi
device usb 2.9 alias usb2_port10 off end
end
chip drivers/usb/acpi
device usb 3.0 alias usb3_port1 off end
end
chip drivers/usb/acpi
device usb 3.1 alias usb3_port2 off end
end
chip drivers/usb/acpi
device usb 3.2 alias usb3_port3 off end
end
chip drivers/usb/acpi
device usb 3.3 alias usb3_port4 off end
end
end
end
end
soc/intel/alderlake: Align chipset.cb with pci_devs.h Refer pci_devs.h naming to align chipset.cb. Correct thc0, thc1 and add cnvi_bt. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Iac33983dc12ed4e5b9257c50d82adc8e4e728ad6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48153 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 14:20:13 +01:00
device pci 14.1 alias usb_otg off end
soc/intel/alderlake: Add initial chipset.cb Similar to the chipset.cb for TGL, this patch gives alias names to all of the published PCI devices. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6576ef4237c1fc8439795ad5b64b1840504edf73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48009 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24 21:48:56 +01:00
device pci 14.2 alias shared_sram off end
device pci 14.3 alias cnvi_wifi off end
device pci 15.0 alias i2c0 off end
device pci 15.1 alias i2c1 off end
device pci 15.2 alias i2c2 off end
device pci 15.3 alias i2c3 off end
device pci 16.0 alias heci1 off end
device pci 16.1 alias heci2 off end
device pci 16.4 alias heci3 off end
device pci 16.5 alias heci4 off end
device pci 17.0 alias sata off end
device pci 19.0 alias i2c4 off end
device pci 19.1 alias i2c5 off end
device pci 19.2 alias uart2 off end
device pci 1c.0 alias pcie_rp1 off end
device pci 1c.1 alias pcie_rp2 off end
device pci 1c.2 alias pcie_rp3 off end
device pci 1c.3 alias pcie_rp4 off end
device pci 1c.4 alias pcie_rp5 off end
device pci 1c.5 alias pcie_rp6 off end
device pci 1c.6 alias pcie_rp7 off end
device pci 1c.7 alias pcie_rp8 off end
device pci 1d.0 alias pcie_rp9 off end
device pci 1d.1 alias pcie_rp10 off end
device pci 1d.2 alias pcie_rp11 off end
device pci 1d.3 alias pcie_rp12 off end
device pci 1e.0 alias uart0 off end
device pci 1e.1 alias uart1 off end
device pci 1e.2 alias gspi0 off end
device pci 1e.3 alias gspi1 off end
device pci 1f.0 alias pch_espi on end
device pci 1f.1 alias p2sb off end
device pci 1f.2 alias pmc hidden end
device pci 1f.3 alias hda off end
device pci 1f.4 alias smbus off end
device pci 1f.5 alias fast_spi on end
device pci 1f.6 alias gbe off end
device pci 1f.7 alias south_tracehub off end
end
end
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