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coreboot-kgpe-d16/src/acpi/dsdt_top.asl

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ACPI: Add top-level ASL Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-21 07:17:00 +01:00
/* SPDX-License-Identifier: GPL-2.0-only */
ACPI: Declare GNVS variables globally There is a common place where acpigen generates these, so the declarations for the OperationRegions should be centralized too. Change-Id: I772492ca9e651b60244c565d1e926dc2ad33cfd8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49795 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-19 13:12:19 +01:00
#include <acpi/acpigen_extern.asl>
ACPI: Separate ChromeOS NVS in ASL For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there is reduced dsdt.aml size and reduced GNVS allocation from cbmem. More importantly, it's less error-prone when the OperationRegion size is not hard-coded inside the .asl files. Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-12 14:23:25 +01:00
ChromeOS: Use CHROMEOS_NVS guard Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where the conditional and dependency are clearly about the presence of an ACPI NVS table specified by vendorcode. For couple locations also CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS). This also helps find some of the CONFIG(CHROMEOS) cases that might be more FMAP and VPD related and not about ChromeOS per-se, as suggested by followup works. Change-Id: Ife888ae43093949bb2d3e397565033037396f434 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 16:53:34 +01:00
#if CONFIG(CHROMEOS_NVS)
ACPI: Move include for <vc/google/chromeos.asl> Change-Id: I4356a8bda71e84afe8c348d366479c5006bf2459 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49796 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-20 22:02:16 +01:00
/* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
ACPI: Separate ChromeOS NVS in ASL For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there is reduced dsdt.aml size and reduced GNVS allocation from cbmem. More importantly, it's less error-prone when the OperationRegion size is not hard-coded inside the .asl files. Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-12 14:23:25 +01:00
#endif
mainboards: Drop PWRS from GNVS Initialize variable to 1 to indicate AC power supply. If platform has EC it will set this correctly based on whether plugged on the charger or not. Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15 12:46:11 +01:00
sb,soc/intel: Drop OSYS from GNVS The value should be set by OSPM using some combination of _OSI() queris in the \_SB._INI() method. To maintain previous behaviour with this commit, boards where GNVS osys initialisation was removed now do the same in ASL. Change-Id: Id4957b12a72fbf7fa988e7ff039e47abcc072e1c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49353 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-29 08:04:30 +01:00
/* Operating system enumeration. */
Name (OSYS, 0)
ACPI: Move PICM declaration Variable PICM was not inside GNVS region and can use a static initialisation value. For most AMD platforms PICM default changes from 1 to 0. Fix comments about PICM==0 used to indicate use of i8259 PIC for interrupt delivery. Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25 16:05:35 +01:00
/* Zero => PIC mode, One => APIC Mode */
Name (PICM, Zero)
mainboards: Drop PWRS from GNVS Initialize variable to 1 to indicate AC power supply. If platform has EC it will set this correctly based on whether plugged on the charger or not. Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15 12:46:11 +01:00
/* Power state (AC = 1) */
Name (PWRS, One)
ACPI: Move common _PIC method Change-Id: I659835354570fb1d4860fcbddf2a51831170a374 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-25 16:05:35 +01:00
/*
* The _PIC method is called by the OS to choose between interrupt
* routing via the i8259 interrupt controller or the APIC.
*
* _PIC is called with a parameter of 0 for i8259 configuration and
* with a parameter of 1 for Local Apic/IOAPIC configuration.
*/
Method (_PIC, 1)
{
/* Remember the OS' IRQ routing choice. */
PICM = Arg0
}
AGESA,binaryPI boards: Move common PCBA in ASL Change-Id: I9d502882c4ddb54af1da42a41591804da2cee0ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-13 23:06:39 +01:00
Rename ECAM-specific MMCONF Kconfigs Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21 00:43:45 +02:00
#if CONFIG(ECAM_MMCONF_SUPPORT)
ACPI: Use common OperationRegion for PCI_MMCONF Change-Id: Iadb4c3c77ecda4df8e48415d246e769ede2ce86d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50648 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 05:58:39 +01:00
Scope(\_SB) {
/* Base address of PCIe config space */
Rename ECAM-specific MMCONF Kconfigs Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21 00:43:45 +02:00
Name(PCBA, CONFIG_ECAM_MMCONF_BASE_ADDRESS)
AGESA,binaryPI boards: Move common PCBA in ASL Change-Id: I9d502882c4ddb54af1da42a41591804da2cee0ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-13 23:06:39 +01:00
ACPI: Use common OperationRegion for PCI_MMCONF Change-Id: Iadb4c3c77ecda4df8e48415d246e769ede2ce86d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50648 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 05:58:39 +01:00
/* Length of PCIe config space, 1MB each bus */
Rename ECAM-specific MMCONF Kconfigs Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21 00:43:45 +02:00
Name(PCLN, CONFIG_ECAM_MMCONF_LENGTH)
ACPI: Use common OperationRegion for PCI_MMCONF Change-Id: Iadb4c3c77ecda4df8e48415d246e769ede2ce86d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50648 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 05:58:39 +01:00
/* PCIe Configuration Space */
OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
}
AGESA,binaryPI boards: Move common PCBA in ASL Change-Id: I9d502882c4ddb54af1da42a41591804da2cee0ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-13 23:06:39 +01:00
#endif