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kbuild: Don't require intel/common changes for every soc In the true spirit of separating components more strictly and allowing to add new components to coreboot without touching existing code, move Intel common code selection to the soc Kconfig and out of src/soc/intel/common/Makefile.inc Change-Id: I0a70656bb9f4550b6088e9f45e68b5106c0eb9af Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10031 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-29 19:45:22 +02:00
config SOC_INTEL_COMMON
bool
help
common code for Intel SOCs
Intel Common SOC: Add romstage support Provide a common romstage implementation for the Intel SOCs. BRANCH=none BUG=None TEST=Build for Braswell Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-21 00:24:54 +02:00
if SOC_INTEL_COMMON
baytrail: Move MRC cache code to a common directory This common code can be shared across Intel SOCs. Change-Id: Id9ec4ccd3fc81cbab19a7d7e13bfa3975d9802d0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196263 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit f9919e2551b02056b83918d2e7b515b25541c583) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6967 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-04-22 19:46:06 +02:00
config CACHE_MRC_SETTINGS
bool "Save cached MRC settings"
default n
if CACHE_MRC_SETTINGS
config MRC_SETTINGS_CACHE_BASE
hex
soc/intel/common: Add mrc.cache file to CBFS when appropriate The code in mrc_cache.c doesn't check for the presence of 'mrc.cache', and just returns hardcoded value for he location of he MRC cache. This becomes a problem when there is a CBFS file at the same location, which can get overwritten. A CBFS file is created to cover this region so that nothing can be added there. This has the advantage of creating a build time error if another cbfs file is hardcoded over the same region. The default location of the MRC cache is also moved to 4G - 128K to ensure that it defaults to something within CBFS. Change-Id: Ic029c182f5a2180cb680e09b25165ee303a448a3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11440 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-28 20:28:35 +02:00
default 0xfffe0000
baytrail: Move MRC cache code to a common directory This common code can be shared across Intel SOCs. Change-Id: Id9ec4ccd3fc81cbab19a7d7e13bfa3975d9802d0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196263 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit f9919e2551b02056b83918d2e7b515b25541c583) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6967 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-04-22 19:46:06 +02:00
config MRC_SETTINGS_CACHE_SIZE
hex
default 0x10000
soc/intel/common: Add function to protect MRC cache Add support for applying write protection to the MRC cache region in SPI flash. This is only enabled if there is write protect GPIO that is set, and the flash status register reports that the flash chip is currently write protected. Then it will call out to a SOC specific function that will enable write protection on the RW_MRC_CACHE region of flash. The implementation is not quite as clean as I would like because there is not a common flash protect interface across SOCs so instead it relies on a new Kconfig variable to be set that will indicate a SOC implements the function to protect a region of SPI flash. BUG=chrome-os-partner:28234 BRANCH=broadwell TEST=build and boot on samus 1) with either WPSW=0 or SRP0=0 the PRR is not applied 2) with both WPSW=1 and SRP0=1 the PRR is applied Change-Id: If5907b7ddf3f966c546ae32dc99aa815beb27587 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a3e0e71dfd7339aab171a26b67aec465a3f332d6 Original-Change-Id: I94e54e4723b1dcdacbb6a05f047d0c0ebc7d8711 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241170 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9494 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-01-16 00:49:07 +01:00
config MRC_SETTINGS_PROTECT
bool "Enable protection on MRC settings"
default n
baytrail: Move MRC cache code to a common directory This common code can be shared across Intel SOCs. Change-Id: Id9ec4ccd3fc81cbab19a7d7e13bfa3975d9802d0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196263 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit f9919e2551b02056b83918d2e7b515b25541c583) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6967 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-04-22 19:46:06 +02:00
endif # CACHE_MRC_SETTINGS
Intel Common SOC: Add romstage support Provide a common romstage implementation for the Intel SOCs. BRANCH=none BUG=None TEST=Build for Braswell Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-21 00:24:54 +02:00
config DISPLAY_MTRRS
soc/intel/common/Kconfig: Fix warning & whitespace Because of a missing close quote, we have the warning: src/soc/intel/common/Kconfig:52:warning:multi-line strings not supported This was added in commit 0946ec37 -Intel Common SOC:Add romstage support The whitespace issue - using spaces instead of a leading tab was added in the same commit. Change-Id: I429c66afb5a7e10ca0e0ef619ac46722c63fb376 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10654 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-06-25 03:04:16 +02:00
bool "MTRRs: Display the MTRR settings"
Intel Common SOC: Add romstage support Provide a common romstage implementation for the Intel SOCs. BRANCH=none BUG=None TEST=Build for Braswell Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-21 00:24:54 +02:00
default n
config DISPLAY_SMM_MEMORY_MAP
bool "SMM: Display the SMM memory map"
default n
soc/intel/common: Add common reset code Move reset support into the Intel common branch. Prevent breaking of existing platforms by using a Kconfig value to select use of the common reset code. BRANCH=none BUG=None TEST=Build and run on Glados Change-Id: I5ba86ef585dde3ef4ecdcc198ab615b5c056d985 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 85d8a6d9628a66cc8d73176d460cd6c5bf6bd6b2 Original-Change-Id: I5048ccf3eb593d59301ad8e808c4e281b9a0aa98 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/248301 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/9505 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-10 06:16:14 +01:00
config SOC_INTEL_COMMON_RESET
bool
default n
Intel Common SOC: Add romstage support Provide a common romstage implementation for the Intel SOCs. BRANCH=none BUG=None TEST=Build for Braswell Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-21 00:24:54 +02:00
intel/common: Add common code for filling out ACPI _SWS Add common code for filling out the NVS fields that are used by the ACPI _SWS methods. The SOC must provide a function to fill out the wake source data since the specific data inputs vary by platform. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I4f3511adcc89a9be5d97a7442055c227a38c5f42 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cee5fa176c16ca44712bce8f3c8045daa5f07339 Original-Change-Id: I16f446ef67777acb57223a84d38062be9f43fcb9 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298167 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11646 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09 01:09:28 +02:00
config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
bool
default n
soc/intel/common: Add LPSS I2C driver Add a generic LPSS I2C driver for Intel SOCs that use the Synopsys DesignWare I2C block and have a similar configuration of that block. This driver is ported from the Chromium depthcharge project where it was ported from U-Boot originally, though it looks very different now. From depthcharge it has been modified to fit into the coreboot I2C driver model with platform_i2c_transfer() and use coreboot semantics throughout including the stopwatch API for timeouts. In order for this shared driver to work the SOC must: 1) Define CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ to set the clock speed that the I2C controller core is running at. 2) Define the lpss_i2c_base_address() function to return the base address for the specified bus. This could be either done by looking up the PCI device or a static table if the controllers are not PCI devices and just have a static base address. The driver is usable in verstage/romstage/ramstage, though it does require early initialization of the controller to set a temporary base address if it is used outside of ramstage. This has been tested on Broadwell and Skylake SOCs in both pre-RAM and ramstage environments by reading and writing both single bytes across multiple segments as well as large blocks of data at once and with different configured bus speeds. While it does need specific configuration for each SOC this driver should be able to work on all Intel SOCs currently in src/soc/intel. Change-Id: Ibe492e53c45edb1d1745ec75e1ff66004081717e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15101 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-07 22:40:11 +02:00
config SOC_INTEL_COMMON_LPSS_I2C
bool
default n
help
This driver supports the Intel Low Power Subsystem (LPSS) I2C
controllers that are based on Synopsys DesignWare IP.
config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ
int
depends on SOC_INTEL_COMMON_LPSS_I2C
help
The clock speed that the I2C controller is running at, in MHz.
No default is set here as this is an SOC-specific value and must
be provided by the SOC when it selects this driver.
intel: Add MMA feature in coreboot This patch implements Memory Margin Analysis feature in coreboot. Few things to note (1) the feature is enabled by setting CONFIG_MMA=y in the config file (2) coreboot reads mma_test_metadata.bin from cbfs during romstage and gets the name of MMA test name and test config name. Then coreboot finds these files in CBFS. If found, coreboot passes location and size of these files to FSP via UPD params. Sets MrcFastBoot to 0 so that MRC happens and then MMA test would be executed during memory init. (3) FSP passes MMA results data in HOB and coreboot saves it in cbmem (4) when system boots to OS after test is executed cbmem tool is used to grab the MMA results data. BRANCH=none BUG=chrome-os-partner:43731 TEST=Build and Boot kunimitsu (FAB3) and executed MMA tests Not tested on Glados CQ-DEPEND=CL:299476,CL:299475,CL:299474,CL:299473,CL:299509,CL:299508,CL:299507,CL:*230478,CL:*230479 Change-Id: I0b4524abcf57db4d2440a06a79b5a0f4b60fa0ea Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4aba9b728c263b9d5da5746ede3807927c9cc2a7 Original-Change-Id: Ie2728154b49eac8695f707127334b12e345398dc Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/299476 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: http://review.coreboot.org/12481 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-11 22:51:38 +02:00
config MMA
soc/intel/common: Fix whitespace in Kconfig Change leading spaces to tabs. Change-Id: Ief138f5f68198578ba9dddb8fbdabbd9a0185a21 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-26 06:33:20 +01:00
bool "enable MMA (Memory Margin Analysis) support"
default n
help
Set this option to y to enable MMA (Memory Margin Analysis) support
intel: Add MMA feature in coreboot This patch implements Memory Margin Analysis feature in coreboot. Few things to note (1) the feature is enabled by setting CONFIG_MMA=y in the config file (2) coreboot reads mma_test_metadata.bin from cbfs during romstage and gets the name of MMA test name and test config name. Then coreboot finds these files in CBFS. If found, coreboot passes location and size of these files to FSP via UPD params. Sets MrcFastBoot to 0 so that MRC happens and then MMA test would be executed during memory init. (3) FSP passes MMA results data in HOB and coreboot saves it in cbmem (4) when system boots to OS after test is executed cbmem tool is used to grab the MMA results data. BRANCH=none BUG=chrome-os-partner:43731 TEST=Build and Boot kunimitsu (FAB3) and executed MMA tests Not tested on Glados CQ-DEPEND=CL:299476,CL:299475,CL:299474,CL:299473,CL:299509,CL:299508,CL:299507,CL:*230478,CL:*230479 Change-Id: I0b4524abcf57db4d2440a06a79b5a0f4b60fa0ea Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4aba9b728c263b9d5da5746ede3807927c9cc2a7 Original-Change-Id: Ie2728154b49eac8695f707127334b12e345398dc Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/299476 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: http://review.coreboot.org/12481 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-11 22:51:38 +02:00
config MMA_BLOBS_PATH
soc/intel/common: Fix whitespace in Kconfig Change leading spaces to tabs. Change-Id: Ief138f5f68198578ba9dddb8fbdabbd9a0185a21 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-26 06:33:20 +01:00
string "Path to MMA blobs"
depends on MMA
default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/mma"
intel: Add MMA feature in coreboot This patch implements Memory Margin Analysis feature in coreboot. Few things to note (1) the feature is enabled by setting CONFIG_MMA=y in the config file (2) coreboot reads mma_test_metadata.bin from cbfs during romstage and gets the name of MMA test name and test config name. Then coreboot finds these files in CBFS. If found, coreboot passes location and size of these files to FSP via UPD params. Sets MrcFastBoot to 0 so that MRC happens and then MMA test would be executed during memory init. (3) FSP passes MMA results data in HOB and coreboot saves it in cbmem (4) when system boots to OS after test is executed cbmem tool is used to grab the MMA results data. BRANCH=none BUG=chrome-os-partner:43731 TEST=Build and Boot kunimitsu (FAB3) and executed MMA tests Not tested on Glados CQ-DEPEND=CL:299476,CL:299475,CL:299474,CL:299473,CL:299509,CL:299508,CL:299507,CL:*230478,CL:*230479 Change-Id: I0b4524abcf57db4d2440a06a79b5a0f4b60fa0ea Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4aba9b728c263b9d5da5746ede3807927c9cc2a7 Original-Change-Id: Ie2728154b49eac8695f707127334b12e345398dc Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/299476 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: http://review.coreboot.org/12481 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-11 22:51:38 +02:00
soc/intel/common: Add utility to load VBT file Change-Id: I8d3d47ca2fc1fc4c10e61c04b941b6378b9c0f80 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14815 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-14 00:27:42 +02:00
config ADD_VBT_DATA_FILE
bool "Add a Video Bios Table (VBT) binary to CBFS"
help
Add a VBT file data file to CBFS. The VBT describes the integrated
GPU and connections, and is needed by FSP in order to initialize the
display.
config VBT_FILE
string "VBT binary path and filename"
depends on ADD_VBT_DATA_FILE
help
The path and filename of the VBT binary.
soc/intel/common: Add IGD OpRegion support Add helper function that fills OpRegion structure based on VBT file content and some reasonable defaults. Change-Id: I9aa8862878cc016a9a684c844ceab390734f3e84 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-13 04:10:11 +02:00
config SOC_INTEL_COMMON_GFX_OPREGION
bool
default n
soc/intel/common: Add common smihandler code Provide default handler for some SMI events. Provide the framework for extracting data from SMM Save State area for processors with SMM revision 30100 and 30101. The SOC specific code should initialize southbridge_smi with event handlers. For SMM Save state handling, SOC code should implement get_smm_save_state_ops which initializes the SOC specific ops for SMM Save State handling. Change-Id: I0aefb6dbb2b1cac5961f9e43f4752b5929235df3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14615 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-05 03:15:49 +02:00
config SOC_INTEL_COMMON_SMI
bool
default n
soc/intel/common: Add common code for acpi c/p/t-state entries Change-Id: I87505bb31cd1b46d27cc5c9ba8d086df7393653e Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-18 22:40:04 +02:00
config SOC_INTEL_COMMON_ACPI
bool
default n
soc/intel/{common,skylake}: provide common NHLT SoC support The nhlt_soc_serialize() and nhlt_soc_serialize_oem_overrides() functions should be able to be leveraged on all Intel SoCs which support NHLT. Therefore provide that functionality and make skylake use it. Change-Id: Ib5535cc874f2680ec22554cecaf97b09753cacd0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15490 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-28 22:41:07 +02:00
config SOC_INTEL_COMMON_NHLT
bool
default n
Intel Common SOC: Add romstage support Provide a common romstage implementation for the Intel SOCs. BRANCH=none BUG=None TEST=Build for Braswell Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-21 00:24:54 +02:00
endif # SOC_INTEL_COMMON
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