2014-10-24 04:14:30 +02:00
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##
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## This file is part of the coreboot project.
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##
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## Copyright 2014 Rockchip Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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2015-08-28 23:34:09 +02:00
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config BOARD_GOOGLE_VEYRON # dummy option to be selected by variant boards
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def_bool n
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if BOARD_GOOGLE_VEYRON
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2014-10-24 04:14:30 +02:00
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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2015-03-30 21:20:55 +02:00
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select BOARD_ID_AUTO
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2014-12-16 01:15:23 +01:00
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select COMMON_CBFS_SPI_WRAPPER
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2014-10-24 04:14:30 +02:00
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_SPI
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2014-11-07 01:51:02 +01:00
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select RAM_CODE_SUPPORT
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2014-10-24 04:14:30 +02:00
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select SOC_ROCKCHIP_RK3288
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2015-08-21 22:37:02 +02:00
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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2014-10-24 04:14:30 +02:00
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select MAINBOARD_DO_NATIVE_VGA_INIT
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select MAINBOARD_HAS_CHROMEOS
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CBFS: Correct ROM_SIZE for ARM boards, use CBFS_SIZE for cbfstool
Some projects (like ChromeOS) put more content than described by CBFS
onto their image. For top-aligned images (read: x86), this has
traditionally been achieved with a CBFS_SIZE Kconfig (which denotes the
area actually managed by CBFS, as opposed to ROM_SIZE) that is used to
calculate the CBFS entry start offset. On bottom-aligned boards, many
define a fake (smaller) ROM_SIZE for only the CBFS part, which is not
consistently done and can be an issue because ROM_SIZE is expected to be
a power of two.
This patch changes all non-x86 boards to describe their actual
(physical) ROM size via one of the BOARD_ROMSIZE_KB_xxx options as a
mainboard Kconfig select (which is the correct place to declare
unchangeable physical properties of the board). It also changes the
cbfstool create invocation to use CBFS_SIZE as the -s parameter for
those architectures, which defaults to ROM_SIZE but gets overridden for
special use cases like ChromeOS. This has the advantage that cbfstool
has a consistent idea of where the area it is responsible for ends,
which offers better bounds-checking and is needed for a subsequent fix.
Also change the FMAP offset to default to right behind the (now
consistently known) CBFS region for non-x86 boards, which has emerged as
a de-facto standard on those architectures and allows us to reduce the
amount of custom configuration. In the future, the nightmare that is
ChromeOS's image build system could be redesigned to enforce this
automatically, and also confirm that it doesn't overwrite any space used
by CBFS (which is now consistently defined as the file size of
coreboot.rom on non-x86).
CQ-DEPEND=CL:231576,CL:231475
BRANCH=None
BUG=chromium:422501
TEST=Built and booted on Veyron_Pinky.
Change-Id: I89aa5b30e25679e074d4cb5eee4c08178892ada6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e707c67c69599274b890d0686522880aa2e16d71
Original-Change-Id: I4fce5a56a8d72f4c4dd3a08c129025f1565351cc
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229974
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9619
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-10 22:11:50 +01:00
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select BOARD_ROMSIZE_KB_4096
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2014-10-24 04:14:30 +02:00
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select HAVE_HARD_RESET
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2014-12-16 01:15:23 +01:00
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select SPI_FLASH
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select SPI_FLASH_GIGADEVICE
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2014-12-19 21:41:16 +01:00
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select SPI_FLASH_WINBOND
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2014-10-24 04:14:30 +02:00
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2015-08-18 22:22:58 +02:00
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config CHROMEOS
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select CHROMEOS_VBNV_EC
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select EC_SOFTWARE_SYNC
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2015-08-24 23:55:29 +02:00
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select VIRTUAL_DEV_SWITCH
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2015-08-18 22:22:58 +02:00
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2014-10-24 04:14:30 +02:00
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config MAINBOARD_DIR
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string
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2015-08-28 23:34:09 +02:00
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default google/veyron
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2014-10-24 04:14:30 +02:00
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config MAINBOARD_PART_NUMBER
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string
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2015-08-28 23:34:09 +02:00
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default "Veyron"
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2014-10-24 04:14:30 +02:00
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config MAINBOARD_VENDOR
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string
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default "Google"
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config EC_GOOGLE_CHROMEEC_SPI_BUS
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hex
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default 0
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config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
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int
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default 100
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config BOOT_MEDIA_SPI_BUS
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2015-04-27 02:53:26 +02:00
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int
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default 2
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2014-10-24 04:14:30 +02:00
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config DRIVER_TPM_I2C_BUS
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hex
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default 0x1
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config DRIVER_TPM_I2C_ADDR
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hex
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default 0x20
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config CONSOLE_SERIAL_UART_ADDRESS
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hex
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2015-04-16 15:27:52 +02:00
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depends on DRIVERS_UART
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2014-10-24 04:14:30 +02:00
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default 0xFF690000
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2015-01-12 22:13:30 +01:00
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config PMIC_BUS
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int
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default 0
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2015-09-16 18:23:23 +02:00
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config CBFS_SIZE
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hex
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default 0x100000 if CHROMEOS
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default ROM_SIZE
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2015-08-28 23:34:09 +02:00
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endif # BOARD_GOOGLE_VEYRON
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