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coreboot-kgpe-d16/src/superio/nuvoton/Makefile.inc

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src/superio: replace license boilerplate with SPDX The authors from the header of the files are added in a previous commit. Change-Id: Iafeaafb9689c65bd2f5de3960097ec0d4c1009e7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38544 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-23 17:12:32 +01:00
# SPDX-License-Identifier: GPL-2.0-only
This is for board Supermicro H8scm. The code was done by existing chips and superiotool. WPCM450 is more like an EC. SuperIO is just a part of multi-features. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-27 18:33:09 +02:00
superio/nuvoton: factor out generic romstage components The romstage of Nuvoton Super I/O chips (but not Nuvoton BMC chips) is identical, so the early_serial.c file can be moved under nuvoton/common. The Nuvoton BMC chip WPCM450 is however left untouched. Change-Id: I4663176c1003b24a49a9fe5f9ebd27a1963b5565 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/5909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-06-01 21:44:43 +02:00
## include generic nuvoton pre-ram stage driver
superio/*: Link early initialization into bootblock This allows to set up the SuperIO in the C_ENVIRONMENT_BOOTBLOCK bootblocks. It is likely unnecessary to do this in verstage. This also renames COMMON_ROMSTAGE to COMMON_PRE_RAM. Change-Id: I3d999611baa1e79c79fe6b1f01822ebaa5f85daf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-04 16:11:50 +01:00
bootblock-$(CONFIG_SUPERIO_NUVOTON_COMMON_PRE_RAM) += common/early_serial.c
romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_PRE_RAM) += common/early_serial.c
superio/nuvoton: factor out generic romstage components The romstage of Nuvoton Super I/O chips (but not Nuvoton BMC chips) is identical, so the early_serial.c file can be moved under nuvoton/common. The Nuvoton BMC chip WPCM450 is however left untouched. Change-Id: I4663176c1003b24a49a9fe5f9ebd27a1963b5565 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/5909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-06-01 21:44:43 +02:00
Do not compile nuvoton superio for all board The nuvoton WPCM450 code is compiled for all boards regardless of whether or not they use it. Compile it only for boards needing it. Change-Id: Iaf4cf2c479eb3238863f0771be799f02a8cc3421 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/129 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-03 16:14:59 +02:00
subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450
Add new superio device - Added in new support for Nuvoton NCT5104D LPC device. Change-Id: I0af8c5e3e46fdd0a549475b30917897ae9e144a7 Signed-off-by: Steven Sherk <steven.sherk@se-eng.com> Reviewed-on: http://review.coreboot.org/3072 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-11 16:40:57 +02:00
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d
src/superio/nuvoton: Add support for NCT5539D Values taken from NCT5539D datasheet V1.1 (June 30th, 2015). Change-Id: I7e979bde53ce3dac1a4f74e7e51a3c6a0149051c Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33842 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-01 15:53:29 +02:00
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += nct5539d
superio/nuvoton: Add support for Nuvoton NCT5572D Change-Id: I3b720cf879bf5326be885d2d3a3f9cfba0a27c7e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/6229 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins)
2014-07-19 00:24:06 +02:00
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += nct5572d
superio/nuvoton/nct6687d: Add early support for NCT6687D Based on the public datasheet of NCT6686 which should be similar to NCT6687D. TEST=Enable serial for debugging on MSI PRO Z690-A WIFI DDR4 and see coreboot console on the debug port Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I0e8744b5958af196de3de63de31852029d81436e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-04-07 15:12:26 +02:00
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d
superio/nuvoton: Add back Nuvoton NCT6776 support Revert commit 53552cc0 (Drop SuperIO nuvoton/nct6776), removing the code as no other mainboard uses it. The board Intel Saddle Brook uses this device, so add the code back with minor adaptations. Change-Id: I546879285ad8336e81798d0fbdf94f72e1fa61a2 Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/16519 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-05 10:00:07 +02:00
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += nct6776
Revert "Drop SuperIO nuvoton/nct6779d" This reverts commit 42444f6f53d47604d9a44c9e109b5717efaed74f. Change-Id: Ifaaaad715d94c3c9ff365745aa2e6ee546924f4f Reviewed-on: http://review.coreboot.org/12328 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-04 21:41:47 +01:00
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d
superio/nuvoton: Add Nuvoton NCT6791D This adds support for Nuvoton NCT6791D Super I/O chips. Makes use of the common Nuvoton early_serial.c. Based on the Datasheet supplied by Nuvoton. Datasheet Version: January 8th, 2016 Revision 1.11 Change-Id: I027d33b85f0dc6ee50deebdccaecc74487eecb40 Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/15967 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-07-29 19:05:33 +02:00
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d
superio/nuvoton: Add support for NPCD378 The NPCD378 can be found on at least: * HP Compaq 8200 * HP Compaq 8300 The datasheet is not publicly available, as HP implements lots of custom hardware. Add basic support for it, based on HP Compaq 8200. The first eight LDNs seem to be standard nuvoton compatible, except for LDN4, which is used to control front LED and power in ACPI S3. LDN8 provides access to HP's proprietary HWM which is accessiable at the LDN's IOBASE with a size of 0x100 bytes. The HWM consists of 16 pages with each holding 0xff bytes. The pages can be selected by writing the page index to IOBASE + 0xff. TODO: Reverse engineer the HWM to support fan control. WARNING: The remaining LDNs have been guessed and might be wrong! The serial has been tested and is working. Change-Id: Ib497fd41b88e9c159eeeffa69bc2bfdccee9cb38 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/25384 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-27 15:58:38 +02:00
subdirs-$(CONFIG_SUPERIO_NUVOTON_NPCD378) += npcd378
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