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coreboot-kgpe-d16/src/drivers/usb/pci_ehci.c

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usbdebug: Split PCI EHCI part There are EHCI compatible host controllers on ARM without PCI bus architecture. Currently we have not come across one with the debug capability though. Change-Id: I8775c9814f6fdf8754f97265118a7186369d721d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5175 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-07 18:24:23 +01:00
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2006 Eric Biederman (ebiederm@xmission.com)
* Copyright (C) 2007 AMD
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stddef.h>
#include <console/console.h>
#include <device/pci_ehci.h>
#include <arch/io.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <string.h>
#include "ehci_debug.h"
#include "ehci.h"
usbdebug: Fix init and add support for postcar It was originally designed such that if usbdebug_init() was called before cbmem_initialize(), it would fetch the already-initialized state from CBMEM. This changed when cbmem_find() behaviour changed to require cbmem_initialize() to be called first. As a result, ramstage had to reinitialize all of the EHCI controller and USB endpoints on entry. This was slow, specially with AMD hardware where one can scan USB ports to probe for the debug dongle. For postcar and ramstage, move usbdebug entry such that it is triggered from CBMEM_INIT_HOOK instead of console_init(). Side-effect of this is usbdebug console shows 'coreboot-xxx ... starting...' line only for romstage. Initialisation for usbdebug is never done in postcar. If you have USBDEBUG_IN_ROMSTAGE=n, postcar will not have console output on usb either. While at it, fix also some other __PRE_RAM__ cases to ENV_ROMSTAGE and alike. Change-Id: If8ab973321a801abc5529f3ff68c5dccae9512ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-07 18:16:27 +02:00
#if ENV_RAMSTAGE
usbdebug: Split PCI EHCI part There are EHCI compatible host controllers on ARM without PCI bus architecture. Currently we have not come across one with the debug capability though. Change-Id: I8775c9814f6fdf8754f97265118a7186369d721d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5175 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-07 18:24:23 +01:00
static struct device_operations *ehci_drv_ops;
static struct device_operations ehci_dbg_ops;
#endif
usbdebug: Remove EHCI_DEBUG_OFFSET Read this variable from PCI configuration capabilities list instead. Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5176 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-09 18:21:30 +01:00
int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset)
usbdebug: Split PCI EHCI part There are EHCI compatible host controllers on ARM without PCI bus architecture. Currently we have not come across one with the debug capability though. Change-Id: I8775c9814f6fdf8754f97265118a7186369d721d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5175 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-07 18:24:23 +01:00
{
pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
usbdebug: Refactor early enable Always sanity check for EHCI class device and move PCI function power enablement up. Change-Id: I1eebe813fbb420738af2d572178213fc660f392a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-07-30 12:23:32 +02:00
usbdebug: Sanity check PCI EHCI location If requested EHCI function is not on bus 0, we would need to open MMIO windows and configuration register space for the connected upstream PCI bridge for it to work. We don't plan to do so. Change-Id: I7c1c60f9d9890dedfedc9d977faf5152ba362692 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06 15:13:07 +01:00
/* We only support controllers on bus 0. */
if (PCI_DEV2SEGBUS(dbg_dev) != 0)
return -1;
usbdebug: Remove EHCI_DEBUG_OFFSET Read this variable from PCI configuration capabilities list instead. Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5176 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-09 18:21:30 +01:00
#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev = dbg_dev;
#else
device: Use pcidev_path_on_root() Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-06-21 15:20:55 +02:00
struct device *dev = pcidev_path_on_root(PCI_DEV2DEVFN(dbg_dev));
usbdebug: Split PCI EHCI part There are EHCI compatible host controllers on ARM without PCI bus architecture. Currently we have not come across one with the debug capability though. Change-Id: I8775c9814f6fdf8754f97265118a7186369d721d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5175 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-07 18:24:23 +01:00
#endif
usbdebug: Remove EHCI_DEBUG_OFFSET Read this variable from PCI configuration capabilities list instead. Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5176 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-09 18:21:30 +01:00
usbdebug: Refactor early enable Always sanity check for EHCI class device and move PCI function power enablement up. Change-Id: I1eebe813fbb420738af2d572178213fc660f392a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-07-30 12:23:32 +02:00
u32 class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
if (class != PCI_EHCI_CLASSCODE)
return -1;
usbdebug: Force EHCI to D0 state When resuming from ACPI S3 suspend, EHCI controller may be in D3 power-management state. Bring it to D0 early so it is functional for console. NOTE: D3hot->D0 transition was observed to reset previous programming of PCI_COMMAND register. Change-Id: Id177ce61926beb057fe67ba42a306d8e565d2657 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-07-30 08:01:24 +02:00
u8 pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM);
if (pm_cap) {
u16 pm_ctrl = pci_read_config16(dev, pm_cap + PCI_PM_CTRL);
/* Set to D0 and disable PM events. */
pm_ctrl &= ~PCI_PM_CTRL_PME_ENABLE;
pm_ctrl &= ~PCI_PM_CTRL_STATE_MASK;
pci_write_config16(dev, pm_cap + PCI_PM_CTRL, pm_ctrl);
}
usbdebug: Remove EHCI_DEBUG_OFFSET Read this variable from PCI configuration capabilities list instead. Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5176 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-09 18:21:30 +01:00
u8 pos = pci_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG);
if (!pos)
return -1;
u32 cap = pci_read_config32(dev, pos);
/* FIXME: We should remove static EHCI_BAR_INDEX. */
usbdebug: Consolidate EHCI_BAR setup There is assumption of static EHCI_BAR_INDEX, try to clean it up by bringing BAR programming at one spot. Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-30 10:37:14 +02:00
u8 ehci_bar = 0x10 + 4 * ((cap >> 29) - 1);
if (ehci_bar != EHCI_BAR_INDEX)
usbdebug: Remove EHCI_DEBUG_OFFSET Read this variable from PCI configuration capabilities list instead. Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5176 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-09 18:21:30 +01:00
return -1;
usbdebug: Consolidate EHCI_BAR setup There is assumption of static EHCI_BAR_INDEX, try to clean it up by bringing BAR programming at one spot. Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-30 10:37:14 +02:00
pci_write_config32(dev, ehci_bar, CONFIG_EHCI_BAR);
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER);
usbdebug: Remove EHCI_DEBUG_OFFSET Read this variable from PCI configuration capabilities list instead. Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5176 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-09 18:21:30 +01:00
*base = CONFIG_EHCI_BAR;
*dbg_offset = (cap>>16) & 0x1ffc;
usbdebug: Consolidate EHCI_BAR setup There is assumption of static EHCI_BAR_INDEX, try to clean it up by bringing BAR programming at one spot. Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-30 10:37:14 +02:00
usbdebug: Remove EHCI_DEBUG_OFFSET Read this variable from PCI configuration capabilities list instead. Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5176 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-09 18:21:30 +01:00
return 0;
usbdebug: Split PCI EHCI part There are EHCI compatible host controllers on ARM without PCI bus architecture. Currently we have not come across one with the debug capability though. Change-Id: I8775c9814f6fdf8754f97265118a7186369d721d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5175 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-07 18:24:23 +01:00
}
void ehci_debug_select_port(unsigned int port)
{
pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
pci_ehci_dbg_set_port(dbg_dev, port);
}
usbdebug: Fix init and add support for postcar It was originally designed such that if usbdebug_init() was called before cbmem_initialize(), it would fetch the already-initialized state from CBMEM. This changed when cbmem_find() behaviour changed to require cbmem_initialize() to be called first. As a result, ramstage had to reinitialize all of the EHCI controller and USB endpoints on entry. This was slow, specially with AMD hardware where one can scan USB ports to probe for the debug dongle. For postcar and ramstage, move usbdebug entry such that it is triggered from CBMEM_INIT_HOOK instead of console_init(). Side-effect of this is usbdebug console shows 'coreboot-xxx ... starting...' line only for romstage. Initialisation for usbdebug is never done in postcar. If you have USBDEBUG_IN_ROMSTAGE=n, postcar will not have console output on usb either. While at it, fix also some other __PRE_RAM__ cases to ENV_ROMSTAGE and alike. Change-Id: If8ab973321a801abc5529f3ff68c5dccae9512ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-07 18:16:27 +02:00
#if ENV_RAMSTAGE
usbdebug: Split PCI EHCI part There are EHCI compatible host controllers on ARM without PCI bus architecture. Currently we have not come across one with the debug capability though. Change-Id: I8775c9814f6fdf8754f97265118a7186369d721d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5175 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-07 18:24:23 +01:00
static void pci_ehci_set_resources(struct device *dev)
{
struct resource *res;
printk(BIOS_DEBUG, "%s EHCI Debug Port hook triggered\n", dev_path(dev));
usbdebug_disable();
if (ehci_drv_ops->set_resources)
ehci_drv_ops->set_resources(dev);
res = find_resource(dev, EHCI_BAR_INDEX);
if (!res)
return;
usbdebug_re_enable((u32)res->base);
report_resource_stored(dev, res, "");
printk(BIOS_DEBUG, "%s EHCI Debug Port relocated\n", dev_path(dev));
}
void pci_ehci_read_resources(struct device *dev)
{
pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
if (!ehci_drv_ops && pci_match_simple_dev(dev, dbg_dev)) {
memcpy(&ehci_dbg_ops, dev->ops, sizeof(ehci_dbg_ops));
ehci_drv_ops = dev->ops;
ehci_dbg_ops.set_resources = pci_ehci_set_resources;
dev->ops = &ehci_dbg_ops;
printk(BIOS_DEBUG, "%s EHCI BAR hook registered\n", dev_path(dev));
} else {
printk(BIOS_DEBUG, "More than one caller of %s from %s\n", __func__, dev_path(dev));
}
pci_dev_read_resources(dev);
}
#endif
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2014-12-25 03:43:20 +01:00
u8 *pci_ehci_base_regs(pci_devfn_t sdev)
usbdebug: Split PCI EHCI part There are EHCI compatible host controllers on ARM without PCI bus architecture. Currently we have not come across one with the debug capability though. Change-Id: I8775c9814f6fdf8754f97265118a7186369d721d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5175 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-07 18:24:23 +01:00
{
#ifdef __SIMPLE_DEVICE__
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2014-12-25 03:43:20 +01:00
u8 *base = (u8 *)(pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f);
usbdebug: Split PCI EHCI part There are EHCI compatible host controllers on ARM without PCI bus architecture. Currently we have not come across one with the debug capability though. Change-Id: I8775c9814f6fdf8754f97265118a7186369d721d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5175 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-07 18:24:23 +01:00
#else
device: Use pcidev_path_on_root() Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-06-21 15:20:55 +02:00
struct device *dev = pcidev_path_on_root(PCI_DEV2DEVFN(sdev));
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2014-12-25 03:43:20 +01:00
u8 *base = (u8 *)(pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f);
usbdebug: Split PCI EHCI part There are EHCI compatible host controllers on ARM without PCI bus architecture. Currently we have not come across one with the debug capability though. Change-Id: I8775c9814f6fdf8754f97265118a7186369d721d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5175 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-07 18:24:23 +01:00
#endif
return base + HC_LENGTH(read32(base));
}
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