2015-05-06 00:07:29 +02:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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2015-04-21 00:20:28 +02:00
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* Copyright (C) 2015 Intel Corp.
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2015-05-06 00:07:29 +02:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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2015-04-21 00:20:28 +02:00
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#include <arch/hlt.h>
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2015-05-06 00:07:29 +02:00
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#include <arch/io.h>
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2019-03-03 07:01:05 +01:00
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#include <device/mmio.h>
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2019-03-01 12:43:02 +01:00
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#include <device/pci_ops.h>
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2015-05-06 00:07:29 +02:00
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#include <console/console.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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2019-08-10 16:27:01 +02:00
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#include <cpu/intel/em64t100_save_state.h>
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2015-05-06 00:07:29 +02:00
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#include <device/pci_def.h>
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#include <elog.h>
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#include <soc/nvs.h>
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2015-04-21 00:20:28 +02:00
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <spi-generic.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <soc/gpio.h>
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2015-05-06 00:07:29 +02:00
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/* GNVS needs to be set by coreboot initiating a software SMI. */
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static global_nvs_t *gnvs;
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static int smm_initialized;
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int southbridge_io_trap_handler(int smif)
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{
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switch (smif) {
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case 0x32:
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printk(BIOS_DEBUG, "OS Init\n");
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2015-04-21 00:20:28 +02:00
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/*
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* gnvs->smif:
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2015-05-06 00:07:29 +02:00
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* On success, the IO Trap Handler returns 0
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* On failure, the IO Trap Handler returns a value != 0
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*/
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gnvs->smif = 0;
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return 1; /* IO trap handled */
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}
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/* Not handled */
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return 0;
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}
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void southbridge_smi_set_eos(void)
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{
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enable_smi(EOS);
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}
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global_nvs_t *smm_get_gnvs(void)
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{
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return gnvs;
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}
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static void busmaster_disable_on_bus(int bus)
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{
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int slot, func;
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unsigned int val;
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unsigned char hdr;
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for (slot = 0; slot < 0x20; slot++) {
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for (func = 0; func < 8; func++) {
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u32 reg32;
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2018-06-10 23:36:44 +02:00
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pci_devfn_t dev = PCI_DEV(bus, slot, func);
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2015-05-06 00:07:29 +02:00
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val = pci_read_config32(dev, PCI_VENDOR_ID);
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if (val == 0xffffffff || val == 0x00000000 ||
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val == 0x0000ffff || val == 0xffff0000)
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continue;
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/* Disable Bus Mastering for this one device */
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 &= ~PCI_COMMAND_MASTER;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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/* If this is a bridge, then follow it. */
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hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
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hdr &= 0x7f;
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if (hdr == PCI_HEADER_TYPE_BRIDGE ||
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hdr == PCI_HEADER_TYPE_CARDBUS) {
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unsigned int buses;
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buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
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busmaster_disable_on_bus((buses >> 8) & 0xff);
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}
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}
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}
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}
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2015-04-21 00:20:28 +02:00
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static void tristate_gpios(uint32_t val)
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{
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/* Tri-state eMMC */
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write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
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SDMMC1_CMD_MMIO_OFFSET, val);
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write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
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SDMMC1_D0_MMIO_OFFSET, val);
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write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
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SDMMC1_D1_MMIO_OFFSET, val);
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write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
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SDMMC1_D2_MMIO_OFFSET, val);
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write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
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SDMMC1_D3_MMIO_OFFSET, val);
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write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
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MMC1_D4_SD_WE_MMIO_OFFSET, val);
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write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
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MMC1_D5_MMIO_OFFSET, val);
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write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
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MMC1_D6_MMIO_OFFSET, val);
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write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
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MMC1_D7_MMIO_OFFSET, val);
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2015-08-10 08:18:23 +02:00
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write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
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MMC1_RCLK_OFFSET, val);
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2015-04-21 00:20:28 +02:00
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/* Tri-state HDMI */
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write32((void *)COMMUNITY_GPNORTH_BASE +
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HV_DDI2_DDC_SDA_MMIO_OFFSET, val);
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write32((void *)COMMUNITY_GPNORTH_BASE +
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HV_DDI2_DDC_SCL_MMIO_OFFSET, val);
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2015-08-11 23:06:15 +02:00
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/* Tri-state CFIO 139 and 140 */
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write32((void *)COMMUNITY_GPSOUTHWEST_BASE +
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CFIO_139_MMIO_OFFSET, val);
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write32((void *)COMMUNITY_GPSOUTHWEST_BASE +
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CFIO_140_MMIO_OFFSET, val);
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2015-04-21 00:20:28 +02:00
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}
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2015-05-06 00:07:29 +02:00
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static void southbridge_smi_sleep(void)
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{
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uint32_t reg32;
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uint8_t slp_typ;
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uint16_t pmbase = get_pmbase();
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/* First, disable further SMIs */
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disable_smi(SLP_SMI_EN);
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/* Figure out SLP_TYP */
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reg32 = inl(pmbase + PM1_CNT);
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printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
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2016-07-14 06:20:26 +02:00
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slp_typ = acpi_sleep_from_pm1(reg32);
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2015-05-06 00:07:29 +02:00
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/* Do any mainboard sleep handling */
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2016-07-14 06:20:26 +02:00
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mainboard_smi_sleep(slp_typ);
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2015-05-06 00:07:29 +02:00
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2019-03-06 01:53:33 +01:00
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#if CONFIG(ELOG_GSMI)
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2015-05-06 00:07:29 +02:00
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/* Log S3, S4, and S5 entry */
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2016-07-14 06:20:26 +02:00
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if (slp_typ >= ACPI_S3)
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elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
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2015-05-06 00:07:29 +02:00
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#endif
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2015-04-21 00:20:28 +02:00
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/* Clear pending GPE events */
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clear_gpe_status();
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2015-05-06 00:07:29 +02:00
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2015-04-21 00:20:28 +02:00
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/* Next, do the deed. */
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2015-05-06 00:07:29 +02:00
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switch (slp_typ) {
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2016-07-14 06:20:26 +02:00
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case ACPI_S0:
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2015-05-06 00:07:29 +02:00
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printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
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break;
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2016-07-14 06:20:26 +02:00
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case ACPI_S1:
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2015-05-06 00:07:29 +02:00
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printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n");
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break;
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2016-07-14 06:20:26 +02:00
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case ACPI_S3:
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2015-05-06 00:07:29 +02:00
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printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
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/* Invalidate the cache before going to S3 */
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wbinvd();
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break;
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2016-07-14 06:20:26 +02:00
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case ACPI_S4:
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2015-05-06 00:07:29 +02:00
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printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n");
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break;
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2016-07-14 06:20:26 +02:00
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case ACPI_S5:
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2015-05-06 00:07:29 +02:00
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printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
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/* Disable all GPE */
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disable_all_gpe();
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/* also iterates over all bridges on bus 0 */
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busmaster_disable_on_bus(0);
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break;
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default:
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printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n");
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break;
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}
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2015-04-21 00:20:28 +02:00
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/* Clear pending wake status bit to avoid immediate wake */
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write32((void *)(0xfed88000 + 0x0200),
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read32((void *)(0xfed88000 + 0x0200)));
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/* Tri-state specific GPIOS to avoid leakage during S3/S5 */
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2016-07-14 06:20:26 +02:00
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if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5))
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2015-04-21 00:20:28 +02:00
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tristate_gpios(PAD_CONTROL_REG0_TRISTATE);
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2015-05-06 00:07:29 +02:00
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2015-04-21 00:20:28 +02:00
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/*
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* Write back to the SLP register to cause the originally intended
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2015-05-06 00:07:29 +02:00
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* event again. We need to set BIT13 (SLP_EN) though to make the
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* sleep happen.
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*/
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enable_pm1_control(SLP_EN);
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/* Make sure to stop executing code here for S3/S4/S5 */
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2016-07-14 06:20:26 +02:00
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if (slp_typ >= ACPI_S3)
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2015-04-21 00:20:28 +02:00
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hlt();
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2015-05-06 00:07:29 +02:00
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2015-04-21 00:20:28 +02:00
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/*
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* In most sleep states, the code flow of this function ends at
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2015-05-06 00:07:29 +02:00
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* the line above. However, if we entered sleep state S1 and wake
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* up again, we will continue to execute code in this function.
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*/
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reg32 = inl(pmbase + PM1_CNT);
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if (reg32 & SCI_EN) {
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/* The OS is not an ACPI OS, so we set the state to S0 */
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disable_pm1_control(SLP_EN | SLP_TYP);
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}
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}
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/*
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* Look for Synchronous IO SMI and use save state from that
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* core in case we are not running on the same core that
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* initiated the IO transaction.
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*/
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static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd)
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{
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em64t100_smm_state_save_area_t *state;
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int node;
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/* Check all nodes looking for the one that issued the IO */
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for (node = 0; node < CONFIG_MAX_CPUS; node++) {
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state = smm_get_save_state(node);
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/* Check for Synchronous IO (bit0==1) */
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if (!(state->io_misc_info & (1 << 0)))
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continue;
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/* Make sure it was a write (bit4==0) */
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if (state->io_misc_info & (1 << 4))
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continue;
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/* Check for APMC IO port */
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if (((state->io_misc_info >> 16) & 0xff) != APM_CNT)
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continue;
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/* Check AX against the requested command */
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if ((state->rax & 0xff) != cmd)
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continue;
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return state;
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}
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return NULL;
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}
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2019-03-06 01:53:33 +01:00
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#if CONFIG(ELOG_GSMI)
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2015-05-06 00:07:29 +02:00
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static void southbridge_smi_gsmi(void)
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{
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u32 *ret, *param;
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uint8_t sub_command;
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em64t100_smm_state_save_area_t *io_smi =
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2018-12-03 16:10:33 +01:00
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smi_apmc_find_state_save(APM_CNT_ELOG_GSMI);
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2015-05-06 00:07:29 +02:00
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if (!io_smi)
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return;
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/* Command and return value in EAX */
|
2015-04-21 00:20:28 +02:00
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ret = (u32 *)&io_smi->rax;
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2015-05-06 00:07:29 +02:00
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sub_command = (uint8_t)(*ret >> 8);
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/* Parameter buffer in EBX */
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2015-04-21 00:20:28 +02:00
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param = (u32 *)&io_smi->rbx;
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2015-05-06 00:07:29 +02:00
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/* drivers/elog/gsmi.c */
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*ret = gsmi_exec(sub_command, param);
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}
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#endif
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static void finalize(void)
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{
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static int finalize_done;
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if (finalize_done) {
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printk(BIOS_DEBUG, "SMM already finalized.\n");
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return;
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}
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finalize_done = 1;
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2019-03-06 01:53:33 +01:00
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#if CONFIG(SPI_FLASH_SMM)
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2015-05-06 00:07:29 +02:00
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/* Re-init SPI driver to handle locked BAR */
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spi_init();
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#endif
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}
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static void southbridge_smi_apmc(void)
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{
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uint8_t reg8;
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em64t100_smm_state_save_area_t *state;
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/* Emulate B2 register as the FADT / Linux expects it */
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reg8 = inb(APM_CNT);
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switch (reg8) {
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case APM_CNT_CST_CONTROL:
|
2015-04-21 00:20:28 +02:00
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/*
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* Calling this function seems to cause
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2015-05-06 00:07:29 +02:00
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* some kind of race condition in Linux
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* and causes a kernel oops
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*/
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printk(BIOS_DEBUG, "C-state control\n");
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break;
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case APM_CNT_PST_CONTROL:
|
2015-04-21 00:20:28 +02:00
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/*
|
|
|
|
* Calling this function seems to cause
|
2015-05-06 00:07:29 +02:00
|
|
|
* some kind of race condition in Linux
|
|
|
|
* and causes a kernel oops
|
|
|
|
*/
|
|
|
|
printk(BIOS_DEBUG, "P-state control\n");
|
|
|
|
break;
|
|
|
|
case APM_CNT_ACPI_DISABLE:
|
|
|
|
disable_pm1_control(SCI_EN);
|
|
|
|
printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
|
|
|
|
break;
|
|
|
|
case APM_CNT_ACPI_ENABLE:
|
|
|
|
enable_pm1_control(SCI_EN);
|
|
|
|
printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
|
|
|
|
break;
|
|
|
|
case APM_CNT_GNVS_UPDATE:
|
|
|
|
if (smm_initialized) {
|
|
|
|
printk(BIOS_DEBUG,
|
|
|
|
"SMI#: SMM structures already initialized!\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
state = smi_apmc_find_state_save(reg8);
|
|
|
|
if (state) {
|
|
|
|
/* EBX in the state save contains the GNVS pointer */
|
|
|
|
gnvs = (global_nvs_t *)((uint32_t)state->rbx);
|
|
|
|
smm_initialized = 1;
|
|
|
|
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
|
|
|
|
}
|
|
|
|
break;
|
2019-03-06 01:53:33 +01:00
|
|
|
#if CONFIG(ELOG_GSMI)
|
2018-12-03 16:10:33 +01:00
|
|
|
case APM_CNT_ELOG_GSMI:
|
2015-05-06 00:07:29 +02:00
|
|
|
southbridge_smi_gsmi();
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
case APM_CNT_FINALIZE:
|
|
|
|
finalize();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
mainboard_smi_apmc(reg8);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void southbridge_smi_pm1(void)
|
|
|
|
{
|
|
|
|
uint16_t pm1_sts = clear_pm1_status();
|
|
|
|
|
2015-04-21 00:20:28 +02:00
|
|
|
/*
|
|
|
|
* While OSPM is not active, poweroff immediately
|
2015-05-06 00:07:29 +02:00
|
|
|
* on a power button event.
|
|
|
|
*/
|
|
|
|
if (pm1_sts & PWRBTN_STS) {
|
2015-04-21 00:20:28 +02:00
|
|
|
/* power button pressed */
|
2019-03-06 01:53:33 +01:00
|
|
|
#if CONFIG(ELOG_GSMI)
|
2015-05-06 00:07:29 +02:00
|
|
|
elog_add_event(ELOG_TYPE_POWER_BUTTON);
|
|
|
|
#endif
|
|
|
|
disable_pm1_control(-1UL);
|
|
|
|
enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void southbridge_smi_gpe0(void)
|
|
|
|
{
|
|
|
|
clear_gpe_status();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void southbridge_smi_tco(void)
|
|
|
|
{
|
|
|
|
uint32_t tco_sts = clear_tco_status();
|
|
|
|
|
|
|
|
/* Any TCO event? */
|
|
|
|
if (!tco_sts)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */
|
|
|
|
/* Handle TCO timeout */
|
|
|
|
printk(BIOS_DEBUG, "TCO Timeout.\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void southbridge_smi_periodic(void)
|
|
|
|
{
|
|
|
|
uint32_t reg32;
|
|
|
|
|
|
|
|
reg32 = inl(get_pmbase() + SMI_EN);
|
|
|
|
|
|
|
|
/* Are periodic SMIs enabled? */
|
|
|
|
if ((reg32 & PERIODIC_EN) == 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
printk(BIOS_DEBUG, "Periodic SMI.\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
typedef void (*smi_handler_t)(void);
|
|
|
|
|
|
|
|
static const smi_handler_t southbridge_smi[32] = {
|
2015-04-21 00:20:28 +02:00
|
|
|
NULL, /* [0] reserved */
|
|
|
|
NULL, /* [1] reserved */
|
|
|
|
NULL, /* [2] BIOS_STS */
|
|
|
|
NULL, /* [3] LEGACY_USB_STS */
|
|
|
|
southbridge_smi_sleep, /* [4] SLP_SMI_STS */
|
|
|
|
southbridge_smi_apmc, /* [5] APM_STS */
|
|
|
|
NULL, /* [6] SWSMI_TMR_STS */
|
|
|
|
NULL, /* [7] reserved */
|
|
|
|
southbridge_smi_pm1, /* [8] PM1_STS */
|
|
|
|
southbridge_smi_gpe0, /* [9] GPE0_STS */
|
|
|
|
NULL, /* [10] reserved */
|
|
|
|
NULL, /* [11] reserved */
|
|
|
|
NULL, /* [12] reserved */
|
|
|
|
southbridge_smi_tco, /* [13] TCO_STS */
|
|
|
|
southbridge_smi_periodic, /* [14] PERIODIC_STS */
|
|
|
|
NULL, /* [15] SERIRQ_SMI_STS */
|
|
|
|
NULL, /* [16] SMBUS_SMI_STS */
|
|
|
|
NULL, /* [17] LEGACY_USB2_STS */
|
|
|
|
NULL, /* [18] INTEL_USB2_STS */
|
|
|
|
NULL, /* [19] reserved */
|
|
|
|
NULL, /* [20] PCI_EXP_SMI_STS */
|
|
|
|
NULL, /* [21] reserved */
|
|
|
|
NULL, /* [22] reserved */
|
|
|
|
NULL, /* [23] reserved */
|
|
|
|
NULL, /* [24] reserved */
|
|
|
|
NULL, /* [25] reserved */
|
|
|
|
NULL, /* [26] SPI_STS */
|
|
|
|
NULL, /* [27] reserved */
|
|
|
|
NULL, /* [28] PUNIT */
|
|
|
|
NULL, /* [29] GUNIT */
|
|
|
|
NULL, /* [30] reserved */
|
|
|
|
NULL /* [31] reserved */
|
2015-05-06 00:07:29 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
void southbridge_smi_handler(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
uint32_t smi_sts;
|
|
|
|
|
2015-04-21 00:20:28 +02:00
|
|
|
/*
|
|
|
|
* We need to clear the SMI status registers, or we won't see what's
|
2015-05-06 00:07:29 +02:00
|
|
|
* happening in the following calls.
|
|
|
|
*/
|
|
|
|
smi_sts = clear_smi_status();
|
|
|
|
|
|
|
|
/* Call SMI sub handler for each of the status bits */
|
|
|
|
for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {
|
|
|
|
if (!(smi_sts & (1 << i)))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (southbridge_smi[i] != NULL) {
|
|
|
|
southbridge_smi[i]();
|
|
|
|
} else {
|
|
|
|
printk(BIOS_DEBUG,
|
2016-01-06 04:58:58 +01:00
|
|
|
"SMI_STS[%d] occurred, but no "
|
2015-05-06 00:07:29 +02:00
|
|
|
"handler available.\n", i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-04-21 00:20:28 +02:00
|
|
|
/*
|
|
|
|
* The GPIO SMI events do not have a status bit in SMI_STS. Therefore,
|
|
|
|
* these events need to be cleared and checked unconditionally.
|
|
|
|
*/
|
2015-05-06 00:07:29 +02:00
|
|
|
mainboard_smi_gpi(clear_alt_status());
|
|
|
|
}
|