2012-07-13 11:36:08 +02:00
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chip northbridge/amd/lx
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2013-02-12 23:17:15 +01:00
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device domain 0 on
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2012-07-13 11:36:08 +02:00
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device pci 1.0 on end # Northbridge
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device pci 1.1 on end # Graphics
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device pci 1.2 on end # AES
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chip southbridge/amd/cs5536
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register "lpc_serirq_enable" = "0x00000000"
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register "lpc_serirq_polarity" = "0x00000000"
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register "lpc_serirq_mode" = "0"
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register "enable_gpio_int_route" = "0x0C0D0700"
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register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
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register "enable_USBP4_device" = "0" #0: host, 1:device
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register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
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register "com1_enable" = "1"
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register "com1_address" = "0x3F8"
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register "com1_irq" = "4"
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register "com2_enable" = "1"
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register "com2_address" = "0x2F8"
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register "com2_irq" = "3"
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register "unwanted_vpci[0]" = "0" # End of list has a zero
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device pci 4.0 on end # Ethernet 0
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2012-09-14 16:28:44 +02:00
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device pci f.0 on # ISA Bridge
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chip drivers/generic/generic # eeprom
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device i2c 52 on end
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end
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end
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2012-07-13 11:36:08 +02:00
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device pci f.2 on end # IDE Controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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device pci f.7 on end # UOC
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end
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end
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# APIC cluster is late CPU init.
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2013-02-13 00:20:54 +01:00
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device cpu_cluster 0 on
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2012-07-13 11:36:08 +02:00
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chip cpu/amd/geode_lx
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device lapic 0 on end
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end
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end
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end
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