coreboot-kgpe-d16/src/northbridge/intel/e7505/Kconfig

# SPDX-License-Identifier: GPL-2.0-only

config NORTHBRIDGE_INTEL_E7505
	bool

if NORTHBRIDGE_INTEL_E7505

config NORTHBRIDGE_SPECIFIC_OPTIONS
	def_bool y
	select NO_MMCONF_SUPPORT
	select HAVE_DEBUG_RAM_SETUP
	select NO_CBFS_MCACHE
	select LEGACY_SMP_INIT

endif
northbridge/*/Kconfig: Replace GPLv2 long form headers with SPDX header Change-Id: Ief2fdedbdba3b7d1708adb2519eb01242e9b52ab Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> 2020-05-07 12:07:24 +02:00			`# SPDX-License-Identifier: GPL-2.0-only`
Intel e7505: enable ECC scrubbing It takes about 3 seconds to scrub 8GiB DDR266 RAM. After ECC scrub XIP cache is disabled for system stability. There is very little to do in romstage after ECC scrub, especially when RAM debug messages are turned off. So the delay caused by this is hardly noticeable. Cache for complete ROM is re-enabled before ramstage is decompressed, and it has no unstability issues. So the code required to re-enable cache for ROM currently already exists in cache-as-ram_ht.inc. A Kconfig option HW_SCRUBBER enables the scrub to be run on hard reboots and power-ons. Change-Id: Icf27acf73240c06b58091f1229efc0f01cca3f85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/905 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> 2012-04-18 19:33:35 +02:00
Add support for E7505 northbridge. Adapted from northbridge/intel/e7501 with only minor changes. This commit provides minimal patch from e7501 and I prefer any cosmetic clean-up to be done after initial merge. Due the incomplete register specifications, it is safer to have e7505 as a separate directory in case I improve it to support wider range of memory configurations. I have no e7501 to test with. Change-Id: Iba3bf9d69ff5e9d9ef3a6ebf8259f048c55d637d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/295 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> 2011-10-31 13:18:33 +01:00			`config NORTHBRIDGE_INTEL_E7505`
copy e7501 component to e7505 Change-Id: Ie69a6b6a040a8b0e7693083b3a2d13c327a165b3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/310 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> 2011-10-21 21:57:59 +02:00			`bool`
Intel e7505: enable ECC scrubbing It takes about 3 seconds to scrub 8GiB DDR266 RAM. After ECC scrub XIP cache is disabled for system stability. There is very little to do in romstage after ECC scrub, especially when RAM debug messages are turned off. So the delay caused by this is hardly noticeable. Cache for complete ROM is re-enabled before ramstage is decompressed, and it has no unstability issues. So the code required to re-enable cache for ROM currently already exists in cache-as-ram_ht.inc. A Kconfig option HW_SCRUBBER enables the scrub to be run on hard reboots and power-ons. Change-Id: Icf27acf73240c06b58091f1229efc0f01cca3f85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/905 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> 2012-04-18 19:33:35 +02:00
			`if NORTHBRIDGE_INTEL_E7505`

treewide [Kconfig]: Remove useless comment Change-Id: I3dafffa61f4fe6089fd11ef6579626aff8088df5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> 2021-02-01 09:45:08 +01:00			`config NORTHBRIDGE_SPECIFIC_OPTIONS`
Intel e7505: enable ECC scrubbing It takes about 3 seconds to scrub 8GiB DDR266 RAM. After ECC scrub XIP cache is disabled for system stability. There is very little to do in romstage after ECC scrub, especially when RAM debug messages are turned off. So the delay caused by this is hardly noticeable. Cache for complete ROM is re-enabled before ramstage is decompressed, and it has no unstability issues. So the code required to re-enable cache for ROM currently already exists in cache-as-ram_ht.inc. A Kconfig option HW_SCRUBBER enables the scrub to be run on hard reboots and power-ons. Change-Id: Icf27acf73240c06b58091f1229efc0f01cca3f85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/905 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> 2012-04-18 19:33:35 +02:00			`def_bool y`
MMCONF_SUPPORT: Flip default to enabled Also remove separate MMCONF_SUPPORT_DEFAULT flag. Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17694 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> 2016-11-29 15:46:56 +01:00			`select NO_MMCONF_SUPPORT`
copy e7501 component to e7505 Change-Id: Ie69a6b6a040a8b0e7693083b3a2d13c327a165b3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/310 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> 2011-10-21 21:57:59 +02:00			`select HAVE_DEBUG_RAM_SETUP`
cbfs: Enable CBFS mcache on most chipsets This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> 2019-10-03 02:28:56 +02:00			`select NO_CBFS_MCACHE`
cpu/x86: Default to PARALLEL_MP selected Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> 2021-05-29 20:23:18 +02:00			`select LEGACY_SMP_INIT`
copy e7501 component to e7505 Change-Id: Ie69a6b6a040a8b0e7693083b3a2d13c327a165b3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/310 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> 2011-10-21 21:57:59 +02:00
Intel e7505: enable ECC scrubbing It takes about 3 seconds to scrub 8GiB DDR266 RAM. After ECC scrub XIP cache is disabled for system stability. There is very little to do in romstage after ECC scrub, especially when RAM debug messages are turned off. So the delay caused by this is hardly noticeable. Cache for complete ROM is re-enabled before ramstage is decompressed, and it has no unstability issues. So the code required to re-enable cache for ROM currently already exists in cache-as-ram_ht.inc. A Kconfig option HW_SCRUBBER enables the scrub to be run on hard reboots and power-ons. Change-Id: Icf27acf73240c06b58091f1229efc0f01cca3f85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/905 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> 2012-04-18 19:33:35 +02:00			`endif`