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coreboot-kgpe-d16/src/soc/intel/baytrail/iosf.c

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baytrail: add initial support The initial Bay Trail code is intended to support the mobile and desktop version of Bay Trail. This support can train memory and execute through ramstage. However, the resource allocation is not curently handled correctly. The MRC cache parameters are successfully saved and reused after the initial cold boot. BUG=chrome-os-partner:22292 BRANCH=None TEST=Built and booted on a reference board through ramstage. Change-Id: I238ede326802aad272c6cca39d7ad4f161d813f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/168387 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4847 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-09-07 07:41:48 +02:00
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <baytrail/iosf.h>
#if !defined(__PRE_RAM__)
#define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12))
static inline void write_iosf_reg(int reg, uint32_t value)
{
write32(IOSF_PCI_BASE + reg, value);
}
static inline uint32_t read_iosf_reg(int reg)
{
return read32(IOSF_PCI_BASE + reg);
}
#else
static inline void write_iosf_reg(int reg, uint32_t value)
{
pci_write_config32(IOSF_PCI_DEV, reg, value);
}
static inline uint32_t read_iosf_reg(int reg)
{
return pci_read_config32(IOSF_PCI_DEV, reg);
}
#endif
uint32_t iosf_bunit_read(int reg)
{
uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_BUNIT) |
IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN;
baytrail: use MCRX in iosf access functions While most registers accesses don't need the use of the MCRX register (upper 24 bits of address) the MCRX register should be protected. The reference code could be doing accesses to registers that initialized the MCRX register. Thus, any access after that should ensure the MCRX register is initialized appropriately. BUG=None BRANCH=None TEST=Verified assembly output. Also, built and booted through depthcharge. Change-Id: I4d6cfbe6bb1666790c69778b8f2c8baeaf015264 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174643 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-10-29 16:57:31 +01:00
write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
baytrail: add initial support The initial Bay Trail code is intended to support the mobile and desktop version of Bay Trail. This support can train memory and execute through ramstage. However, the resource allocation is not curently handled correctly. The MRC cache parameters are successfully saved and reused after the initial cold boot. BUG=chrome-os-partner:22292 BRANCH=None TEST=Built and booted on a reference board through ramstage. Change-Id: I238ede326802aad272c6cca39d7ad4f161d813f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/168387 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4847 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-09-07 07:41:48 +02:00
write_iosf_reg(MCR_REG, cr);
return read_iosf_reg(MDR_REG);
}
void iosf_bunit_write(int reg, uint32_t val)
{
uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) |
IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN;
write_iosf_reg(MDR_REG, val);
baytrail: use MCRX in iosf access functions While most registers accesses don't need the use of the MCRX register (upper 24 bits of address) the MCRX register should be protected. The reference code could be doing accesses to registers that initialized the MCRX register. Thus, any access after that should ensure the MCRX register is initialized appropriately. BUG=None BRANCH=None TEST=Verified assembly output. Also, built and booted through depthcharge. Change-Id: I4d6cfbe6bb1666790c69778b8f2c8baeaf015264 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174643 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-10-29 16:57:31 +01:00
write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
baytrail: IOSF write functions need to set data before control The data needs to be available in the register before the control bits are set to make the write happen. BUG=chrome-os-partner:23507 BRANCH=rambi TEST=successfully ungate power on PUNIT on rambi Change-Id: I8fae60d5385ce9a401c1dec9cbb39b70d157a6c2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174898 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4906 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-28 22:18:38 +01:00
write_iosf_reg(MCR_REG, cr);
baytrail: add initial support The initial Bay Trail code is intended to support the mobile and desktop version of Bay Trail. This support can train memory and execute through ramstage. However, the resource allocation is not curently handled correctly. The MRC cache parameters are successfully saved and reused after the initial cold boot. BUG=chrome-os-partner:22292 BRANCH=None TEST=Built and booted on a reference board through ramstage. Change-Id: I238ede326802aad272c6cca39d7ad4f161d813f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/168387 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4847 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-09-07 07:41:48 +02:00
}
baytrail: add dunit access and registers The dunit on baytrail is the dram unit. Provide a means to access the configuration registers there using the proper IOSF mechanisms. BUG=chrome-os-partner:22875 BRANCH=none TEST=Built and booted. Able to read dram registers. Change-Id: I4d5c019720a7883fe93f3e1860bcd57ce2ea6542 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170490 Reviewed-on: http://review.coreboot.org/4853 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-23 21:17:35 +02:00
uint32_t iosf_dunit_read(int reg)
{
uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) |
IOSF_PORT(IOSF_PORT_SYSMEMC) | IOSF_REG(reg) |
IOSF_BYTE_EN;
baytrail: use MCRX in iosf access functions While most registers accesses don't need the use of the MCRX register (upper 24 bits of address) the MCRX register should be protected. The reference code could be doing accesses to registers that initialized the MCRX register. Thus, any access after that should ensure the MCRX register is initialized appropriately. BUG=None BRANCH=None TEST=Verified assembly output. Also, built and booted through depthcharge. Change-Id: I4d6cfbe6bb1666790c69778b8f2c8baeaf015264 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174643 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-10-29 16:57:31 +01:00
write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
baytrail: add dunit access and registers The dunit on baytrail is the dram unit. Provide a means to access the configuration registers there using the proper IOSF mechanisms. BUG=chrome-os-partner:22875 BRANCH=none TEST=Built and booted. Able to read dram registers. Change-Id: I4d5c019720a7883fe93f3e1860bcd57ce2ea6542 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170490 Reviewed-on: http://review.coreboot.org/4853 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-23 21:17:35 +02:00
write_iosf_reg(MCR_REG, cr);
return read_iosf_reg(MDR_REG);
}
baytrail: print dram configuration After running the MRC blob print out some information on the training: MRC version, number channels, DDR3 type, and DRAM frequency. Example output: MRC v0.90 2 channels of DDR3 @ 1066MHz Apparently there are two dunit IOSF ports -- 1 for each channel. However, certain registers really on live in channel 0. Thus, there was some changes to dunit support in the iosf area. BUG=chrome-os-partner:22875 BRANCH=None TEST=Built and booted bayleybay in different configs. Change-Id: Ib306432b55f9222b4eb3d14b2467bc0e7617e24f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172770 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4882 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-10-11 07:26:04 +02:00
uint32_t iosf_dunit_ch0_read(int reg)
{
return iosf_dunit_read(reg);
}
uint32_t iosf_dunit_ch1_read(int reg)
{
uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) |
IOSF_PORT(IOSF_PORT_DUNIT_CH1) | IOSF_REG(reg) |
IOSF_BYTE_EN;
baytrail: use MCRX in iosf access functions While most registers accesses don't need the use of the MCRX register (upper 24 bits of address) the MCRX register should be protected. The reference code could be doing accesses to registers that initialized the MCRX register. Thus, any access after that should ensure the MCRX register is initialized appropriately. BUG=None BRANCH=None TEST=Verified assembly output. Also, built and booted through depthcharge. Change-Id: I4d6cfbe6bb1666790c69778b8f2c8baeaf015264 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174643 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-10-29 16:57:31 +01:00
write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
baytrail: print dram configuration After running the MRC blob print out some information on the training: MRC version, number channels, DDR3 type, and DRAM frequency. Example output: MRC v0.90 2 channels of DDR3 @ 1066MHz Apparently there are two dunit IOSF ports -- 1 for each channel. However, certain registers really on live in channel 0. Thus, there was some changes to dunit support in the iosf area. BUG=chrome-os-partner:22875 BRANCH=None TEST=Built and booted bayleybay in different configs. Change-Id: Ib306432b55f9222b4eb3d14b2467bc0e7617e24f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172770 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4882 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-10-11 07:26:04 +02:00
write_iosf_reg(MCR_REG, cr);
return read_iosf_reg(MDR_REG);
}
baytrail: add dunit access and registers The dunit on baytrail is the dram unit. Provide a means to access the configuration registers there using the proper IOSF mechanisms. BUG=chrome-os-partner:22875 BRANCH=none TEST=Built and booted. Able to read dram registers. Change-Id: I4d5c019720a7883fe93f3e1860bcd57ce2ea6542 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170490 Reviewed-on: http://review.coreboot.org/4853 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-23 21:17:35 +02:00
void iosf_dunit_write(int reg, uint32_t val)
{
uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_SYSMEMC) |
IOSF_PORT(IOSF_PORT_SYSMEMC) | IOSF_REG(reg) |
IOSF_BYTE_EN;
baytrail: add punit access functions Like the bunit and dunit, add the punit accessor functions. BUG=chrome-os-partner:23085 BRANCH=None TEST=Built. Change-Id: Ifd7184dfca8c0491c107bc1c562ea1ded444e372 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171931 Reviewed-on: http://review.coreboot.org/4867 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-10-04 22:23:31 +02:00
write_iosf_reg(MDR_REG, val);
baytrail: use MCRX in iosf access functions While most registers accesses don't need the use of the MCRX register (upper 24 bits of address) the MCRX register should be protected. The reference code could be doing accesses to registers that initialized the MCRX register. Thus, any access after that should ensure the MCRX register is initialized appropriately. BUG=None BRANCH=None TEST=Verified assembly output. Also, built and booted through depthcharge. Change-Id: I4d6cfbe6bb1666790c69778b8f2c8baeaf015264 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174643 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-10-29 16:57:31 +01:00
write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
baytrail: IOSF write functions need to set data before control The data needs to be available in the register before the control bits are set to make the write happen. BUG=chrome-os-partner:23507 BRANCH=rambi TEST=successfully ungate power on PUNIT on rambi Change-Id: I8fae60d5385ce9a401c1dec9cbb39b70d157a6c2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174898 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4906 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-28 22:18:38 +01:00
write_iosf_reg(MCR_REG, cr);
baytrail: add punit access functions Like the bunit and dunit, add the punit accessor functions. BUG=chrome-os-partner:23085 BRANCH=None TEST=Built. Change-Id: Ifd7184dfca8c0491c107bc1c562ea1ded444e372 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171931 Reviewed-on: http://review.coreboot.org/4867 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-10-04 22:23:31 +02:00
}
uint32_t iosf_punit_read(int reg)
{
uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_PMC) |
IOSF_PORT(IOSF_PORT_PMC) | IOSF_REG(reg) |
IOSF_BYTE_EN;
baytrail: use MCRX in iosf access functions While most registers accesses don't need the use of the MCRX register (upper 24 bits of address) the MCRX register should be protected. The reference code could be doing accesses to registers that initialized the MCRX register. Thus, any access after that should ensure the MCRX register is initialized appropriately. BUG=None BRANCH=None TEST=Verified assembly output. Also, built and booted through depthcharge. Change-Id: I4d6cfbe6bb1666790c69778b8f2c8baeaf015264 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174643 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-10-29 16:57:31 +01:00
write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
baytrail: add punit access functions Like the bunit and dunit, add the punit accessor functions. BUG=chrome-os-partner:23085 BRANCH=None TEST=Built. Change-Id: Ifd7184dfca8c0491c107bc1c562ea1ded444e372 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171931 Reviewed-on: http://review.coreboot.org/4867 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-10-04 22:23:31 +02:00
write_iosf_reg(MCR_REG, cr);
return read_iosf_reg(MDR_REG);
}
void iosf_punit_write(int reg, uint32_t val)
{
uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_PMC) |
IOSF_PORT(IOSF_PORT_PMC) | IOSF_REG(reg) |
IOSF_BYTE_EN;
baytrail: add dunit access and registers The dunit on baytrail is the dram unit. Provide a means to access the configuration registers there using the proper IOSF mechanisms. BUG=chrome-os-partner:22875 BRANCH=none TEST=Built and booted. Able to read dram registers. Change-Id: I4d5c019720a7883fe93f3e1860bcd57ce2ea6542 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170490 Reviewed-on: http://review.coreboot.org/4853 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-23 21:17:35 +02:00
write_iosf_reg(MDR_REG, val);
baytrail: use MCRX in iosf access functions While most registers accesses don't need the use of the MCRX register (upper 24 bits of address) the MCRX register should be protected. The reference code could be doing accesses to registers that initialized the MCRX register. Thus, any access after that should ensure the MCRX register is initialized appropriately. BUG=None BRANCH=None TEST=Verified assembly output. Also, built and booted through depthcharge. Change-Id: I4d6cfbe6bb1666790c69778b8f2c8baeaf015264 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174643 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-10-29 16:57:31 +01:00
write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
baytrail: IOSF write functions need to set data before control The data needs to be available in the register before the control bits are set to make the write happen. BUG=chrome-os-partner:23507 BRANCH=rambi TEST=successfully ungate power on PUNIT on rambi Change-Id: I8fae60d5385ce9a401c1dec9cbb39b70d157a6c2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174898 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4906 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-28 22:18:38 +01:00
write_iosf_reg(MCR_REG, cr);
baytrail: add dunit access and registers The dunit on baytrail is the dram unit. Provide a means to access the configuration registers there using the proper IOSF mechanisms. BUG=chrome-os-partner:22875 BRANCH=none TEST=Built and booted. Able to read dram registers. Change-Id: I4d5c019720a7883fe93f3e1860bcd57ce2ea6542 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170490 Reviewed-on: http://review.coreboot.org/4853 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-23 21:17:35 +02:00
}
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