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< head >
< title > SoC< / title >
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< h1 > x86 System on a Chip (SoC) Development< / h1 >
< p >
SoC development is best done in parallel with development for a specific
board. The combined steps are listed
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< a target = "_blank" href = "../development.html" > here< / a > .
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The development steps for the SoC are listed below:
< / p >
< ol >
< li > < a target = "_blank" href = "../fsp1_1.html#RequiredFiles" > FSP 1.1< / a > required files< / li >
< li > SoC < a href = "#RequiredFiles" > Required Files< / a > < / li >
< li > < a href = "#Descriptor" > Start Booting< / a > < / li >
< li > < a href = "#EarlyDebug" > Early Debug< / a > < / li >
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< li > < a href = "#Bootblock" > Bootblock< / a > < / li >
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< li > < a href = "#TempRamInit" > TempRamInit< / a > < / li >
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< li > < a href = "#Romstage" > Romstage< / a >
< ol type = "A" >
< li > Enable < a href = "#SerialOutput" > Serial Output"< / a > < / li >
< / ol >
< / li >
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< / ol >
< hr >
< h1 > < a name = "RequiredFiles" > Required Files< / a > < / h1 >
< p >
Create the directory as src/soc/< Vendor> /< Chip Family> .
< / p >
< p >
The following files are required to build a new SoC:
< / p >
< ul >
< li > Include files
< ul >
< li > include/soc/pei_data.h< / li >
< li > include/soc/pm.h< / li >
< / ul >
< / li >
< li > Kconfig - Defines the Kconfig value for the SoC and selects the tool
chains for the various stages:
< ul >
< li > select ARCH_BOOTBLOCK_< Tool Chain> < / li >
< li > select ARCH_RAMSTAGE_< Tool Chain> < / li >
< li > select ARCH_ROMSTAGE_< Tool Chain> < / li >
< li > select ARCH_VERSTAGE_< Tool Chain> < / li >
< / ul >
< / li >
< li > Makefile.inc - Specify the include paths< / li >
< li > memmap.c - Top of usable RAM< / li >
< / ul >
< hr >
< h1 > < a name = "Descriptor" > Start Booting< / a > < / h1 >
< p >
Some SoC parts require additional firmware components in the flash.
This section describes how to add those pieces.
< / p >
< h2 > Intel Firmware Descriptor< / h2 >
< p >
The Intel Firmware Descriptor (IFD) is located at the base of the flash part.
The following command overwrites the base of the flash image with the Intel
Firmware Descriptor:
< / p >
< pre > < code > dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>& 1< / code > < / pre >
< h2 > < a name = "MEB" > Management Engine Binary< / a > < / h2 >
< p >
Some SoC parts contain and require that the Management Engine (ME) be running
before it is possible to bring the x86 processor out of reset. A binary file
containing the management engine code must be added to the firmware using the
ifdtool. The following commands add this binary blob:
< / p >
< pre > < code > util/ifdtool/ifdtool -i ME:me.bin build/coreboot.rom
mv build/coreboot.rom.new build/coreboot.rom
< / code > < / pre >
< h2 > < a name = "EarlyDebug" > Early Debug< / a > < / h2 >
< p >
Early debugging between the reset vector and the time the serial port is enabled
is most easily done by writing values to port 0x80.
< / p >
< h2 > Success< / h2 >
< p >
When the reset vector is successfully invoked, port 0x80 will output the following value:
< / p >
< ul >
< li > 0x01: < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45" > POST_RESET_VECTOR_CORRECT< / a >
- Bootblock successfully executed the
< a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4" > reset vector< / a >
and entered the 16-bit code at
< a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35" > _start< / a >
< / li >
< / ul >
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< hr >
< h1 > < a name = "Bootblock" > Bootblock< / a > < / h1 >
< p >
Implement the bootblock using the following steps:
< / p >
< ol >
< li > Create the directory as src/soc/< Vendor> /< Chip Family> /bootblock< / li >
< li > Add the timestamp.inc file which initializes the floating point registers and saves
the initial timestamp.
< / li >
< li > Add the bootblock.c file which:
< ol type = "A" >
< li > Enables memory-mapped PCI config access< / li >
< li > Updates the microcode by calling intel_update_microcode_from_cbfs< / li >
< li > Enable ROM caching< / li >
< / ol >
< / li >
< li > Edit the src/soc/< Vendor> /< Chip Family> /Kconfig file
< ol type = "A" >
< li > Add the BOOTBLOCK_CPU_INIT value to point to the bootblock.c file< / li >
< li > Add the CHIPSET_BOOTBLOCK_INCLUDE value to point to the timestamp.inc file< / li >
< / ol >
< / li >
< li > Edit the src/soc/< Vendor> /< Chip Family> /Makefile.inc file
< ol type = "A" >
< li > Add the bootblock subdirectory< / li >
< / ol >
< / li >
< li > Edit the src/soc/< Vendor> /< Chip Family> /memmap.c file
< ol type = "A" >
< li > Add the fsp/memmap.h include file< / li >
< li > Add the mmap_region_granularity routine< / li >
< / ol >
< / li >
< li > Add the necessary .h files to define the necessary values and structures< / li >
< li > When successful port 0x80 will output the following values:
< ol type = "A" >
< li > 0x01: < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45" > POST_RESET_VECTOR_CORRECT< / a >
- Bootblock successfully executed the
< a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4" > reset vector< / a >
and entered the 16-bit code at
< a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35" > _start< / a >
< / li >
< li > 0x10: < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l53" > POST_ENTER_PROTECTED_MODE< / a >
- Bootblock executing in
< a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc;hb=HEAD#l55" > 32-bit mode< / a >
< / li >
< li > 0x10 - Verstage/romstage reached 32-bit mode< / li >
< / ol >
< / li >
< / ol >
< p >
< b > Build Note:< / b > The following files are included into the default bootblock image:
< / p >
< ul >
< li > < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S;hb=HEAD" > src/arch/x86/bootblock_romcc.S< / a >
added by < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l133" > src/arch/x86/Makefile.inc< / a >
and includes the following files:
< ul >
< li > < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/prologue.inc" > src/arch/x86/prologue.inc< / a > < / li >
< li > < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc" > src/cpu/x86/16bit/reset16.inc< / a > < / li >
< li > < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc" > src/cpu/x86/16bit/entry16.inc< / a > < / li >
< li > < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc" > src/cpu/x86/32bit/entry32.inc< / a > < / li >
< li > The code in
< a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S" > src/arch/x86/bootblock_romcc.S< / a >
includes src/soc/< Vendor> /< Chip Family> /bootblock/timestamp.inc using the
CONFIG_CHIPSET_BOOTBLOCK_INCLUDE value set above
< / li >
< li > < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/sse_enable.inc" > src/cpu/x86/sse_enable.inc< / a > < / li >
< li > The code in
< a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l156" > src/arch/x86/Makefile.inc< / a >
invokes the ROMCC tool to convert the following "C" code into assembler as bootblock.inc:
< ul >
< li > < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/arch/bootblock_romcc.h" > src/arch/x86/include/arch/bootblock_romcc.h< / a > < / li >
< li > < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/lapic/boot_cpu.c" > src/cpu/x86/lapic/boot_cpu.c< / a > < / li >
< li > The CONFIG_BOOTBLOCK_CPU_INIT value set above typically points to the code in
src/soc/< Vendor> /< Chip Family> /bootblock/bootblock.c
< / li >
< / ul >
< / li >
< / ul >
< / li >
< li > < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/id.S" > src/arch/x86/id.S< / a >
added by < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l110" > src/arch/x86/Makefile.inc< / a >
< / li >
< li > < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/fit.S" > src/cpu/intel/fit/fit.S< / a >
added by < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/Makefile.inc;hb=HEAD" > src/cpu/intel/fit/Makefile.inc< / a >
< / li >
< li > < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/walkcbfs.S" > src/arch/x86/walkcbfs.S< / a >
added by < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l137" > src/arch/x86/Makefile.inc< / a >
< / li >
< / ul >
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< hr >
< h1 > < a name = "TempRamInit" > TempRamInit< / a > < / h1 >
< p >
Enable the call to TempRamInit in two stages:
< / p >
< ol >
< li > Finding the FSP binary in the read-only CBFS region< / li >
< li > Call TempRamInit< / li >
< / ol >
< h2 > Find FSP Binary< / h2 >
< p >
Use the following steps to locate the FSP binary:
< / p >
< ol >
< li > Edit the src/soc/< Vendor> /< Chip Family> /Kconfig file
< ol type = "A" >
< li > Add "select USE_GENERIC_FSP_CAR_INC" to enable the use of
< a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc" > src/drivers/intel/fsp1_1/cache_as_ram.inc< / a >
< / li >
< li > Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common
specifically building
< a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/common/util.c" > util.c< / a >
< / li >
< / ol >
< / li >
< li > Debug the result until port 0x80 outputs
< ol type = "A" >
< li > 0x90: < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205" > POST_FSP_TEMP_RAM_INIT< / a >
- Just before calling
< a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73" > TempRamInit< / a >
< / li >
< li > Alternating 0xba and 0x01 - The FSP image was not found< / li >
< / ol >
< / li >
< li > Add the < a target = "_blank" href = "../fsp1_1.html#FspBinary" > FSP binary file< / a > to the flash image< / li >
< li > Set the following Kconfig values:
< ul >
< li > CONFIG_FSP_LOC to the FSP base address specified in the previous step< / li >
< li > CONFIG_FSP_IMAGE_ID_STRING< / li >
< / ul >
< / li >
< li > Debug the result until port 0x80 outputs
< ol type = "A" >
< li > 0x90: < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205" > POST_FSP_TEMP_RAM_INIT< / a >
- Just before calling
< a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73" > TempRamInit< / a >
< / li >
< li > Alternating 0xbb and 0x02 - TempRamInit executed, no CPU microcode update found< / li >
< / ol >
< / li >
< / ol >
< h2 > Calling TempRamInit< / h2 >
< p >
Use the following steps to debug the call to TempRamInit:
< / p >
< ol >
< li > Add the CPU microcode update file
< ol type = "A" >
< li > Add the microcode file with the following command
< pre > < code > util/cbfstool/cbfstool build/coreboot.rom add -t microcode -n cpu_microcode_blob.bin -b < base address> -f cpu_microcode_blob.bin< / code > < / pre >
< / li >
< li > Set the Kconfig values
< ul >
< li > CONFIG_CPU_MICROCODE_CBFS_LOC set to the value from the previous step< / li >
< li > CONFIG_CPU_MICROCODE_CBFS_LEN< / li >
< / ul >
< / li >
< / ol >
< / li >
< li > Debug the result until port 0x80 outputs
< ol type = "A" >
< li > 0x90: < a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205" > POST_FSP_TEMP_RAM_INIT< / a >
- Just before calling
< a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73" > TempRamInit< / a >
< / li >
< li > 0x2A - Just before calling
< a target = "_blank" href = "http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151" > cache_as_ram_main< / a >
which is the start of the verstage code which may be part of romstage
< / li >
< / ol >
< / li >
< / ol >
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< hr >
< h1 > < a name = "Romstage" > Romstage< / a > < / h1 >
< h2 > < a name = "SerialOutput" > Serial Output< / a > < / h2 >
< p >
The following steps add the serial output support for romstage:
< / p >
< ol >
< li > Create the romstage subdirectory< / li >
< li > Add romstage/romstage.c
< ol type = "A" >
< li > Program the necessary base addresses< / li >
< li > Disable the TCO< / li >
< / ol >
< / li >
< li > Add romstage/Makefile.inc
< ol type = "A" >
< li > Add romstage.c to romstage< / li >
< / ol >
< / li >
< li > Add gpio configuration support if necessary< / li >
< li > Add the necessary .h files to support the build< / li >
< li > Update Makefile.inc
< ol type = "A" >
< li > Add the romstage subdirectory< / li >
< li > Add the gpio configuration support file to romstage< / li >
< / ol >
< / li >
< li > Set the necessary Kconfig values to enable serial output:
< ul >
< li > CONFIG_DRIVERS_UART_< driver> =y< / li >
< li > CONFIG_CONSOLE_SERIAL=y< / li >
< li > CONFIG_UART_FOR_CONSOLE=< port> < / li >
< li > CONFIG_CONSOLE_SERIAL_115200=y< / li >
< / ul >
< / li >
< / ol >
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< hr >
< p > Modified: 31 January 2016< / p >
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