2022-08-11 10:27:10 +02:00
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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2021-01-07 13:25:54 +01:00
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2021-08-10 06:39:32 +02:00
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#include <bootmem.h>
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2022-07-19 11:09:39 +02:00
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#include <console/console.h>
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2021-01-07 13:25:54 +01:00
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#include <device/device.h>
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2021-07-14 09:41:20 +02:00
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#include <device/pci.h>
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2021-06-25 17:27:56 +02:00
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#include <soc/apusys.h>
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2022-12-20 08:30:38 +01:00
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#include <soc/apusys_devapc.h>
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2021-06-21 03:13:19 +02:00
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#include <soc/devapc.h>
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2021-08-10 06:39:32 +02:00
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#include <soc/dfd.h>
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2021-01-07 13:25:54 +01:00
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#include <soc/emi.h>
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2021-08-13 10:34:26 +02:00
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#include <soc/hdmi.h>
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2021-05-17 15:58:55 +02:00
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#include <soc/mcupm.h>
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2021-03-25 10:50:14 +01:00
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#include <soc/mmu_operations.h>
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2021-07-14 09:41:20 +02:00
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#include <soc/pcie.h>
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2021-05-03 14:44:09 +02:00
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#include <soc/sspm.h>
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2021-04-19 10:06:55 +02:00
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#include <soc/ufs.h>
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2021-01-07 13:25:54 +01:00
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#include <symbols.h>
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2021-08-10 06:39:32 +02:00
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void bootmem_platform_add_ranges(void)
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{
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if (CONFIG(MTK_DFD))
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bootmem_add_range(DFD_DUMP_ADDRESS, DFD_DUMP_SIZE, BM_MEM_RESERVED);
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}
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2021-01-07 13:25:54 +01:00
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static void soc_read_resources(struct device *dev)
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{
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2022-06-20 13:13:36 +02:00
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ram_range(dev, 0, (uintptr_t)_dram, sdram_size());
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2021-01-07 13:25:54 +01:00
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}
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static void soc_init(struct device *dev)
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{
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2021-03-25 10:50:14 +01:00
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mtk_mmu_disable_l2c_sram();
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2021-06-21 03:13:19 +02:00
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dapc_init();
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2022-12-20 08:30:38 +01:00
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start_apusys_devapc();
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2021-06-25 17:27:56 +02:00
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apusys_init();
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2021-05-17 15:58:55 +02:00
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mcupm_init();
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2021-05-03 14:44:09 +02:00
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sspm_init();
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2021-08-10 06:39:32 +02:00
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if (CONFIG(MTK_DFD))
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dfd_init();
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2021-04-19 10:06:55 +02:00
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ufs_disable_refclk();
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2021-08-13 10:34:26 +02:00
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hdmi_low_power_setting();
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2021-01-07 13:25:54 +01:00
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}
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static struct device_operations soc_ops = {
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.read_resources = soc_read_resources,
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2022-03-14 09:53:59 +01:00
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.set_resources = noop_set_resources,
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2021-01-07 13:25:54 +01:00
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.init = soc_init,
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};
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2021-07-14 09:41:20 +02:00
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static struct device_operations pci_domain_ops = {
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.read_resources = &mtk_pcie_domain_read_resources,
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.set_resources = &mtk_pcie_domain_set_resources,
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.scan_bus = &pci_domain_scan_bus,
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.enable = &mtk_pcie_domain_enable,
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};
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2021-01-07 13:25:54 +01:00
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static void enable_soc_dev(struct device *dev)
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{
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if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
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dev->ops = &soc_ops;
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2022-07-19 11:09:39 +02:00
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else if (dev->path.type == DEVICE_PATH_DOMAIN) {
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if (mainboard_needs_pcie_init())
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dev->ops = &pci_domain_ops;
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else
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printk(BIOS_DEBUG, "Skip setting PCIe ops\n");
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}
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2021-01-07 13:25:54 +01:00
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}
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struct chip_operations soc_mediatek_mt8195_ops = {
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CHIP_NAME("SOC Mediatek MT8195")
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.enable_dev = enable_soc_dev,
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};
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