2019-05-10 15:52:00 +02:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2016 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0 and up
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 // OEM revision
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)
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{
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// Some generic macros
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#include <soc/intel/skylake/acpi/platform.asl>
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// global NVS and variables
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#include <soc/intel/skylake/acpi/globalnvs.asl>
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// CPU
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#include <cpu/intel/common/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/skylake/acpi/systemagent.asl>
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#include <soc/intel/skylake/acpi/pch.asl>
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}
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}
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// Chipset specific sleep states
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2019-10-30 12:18:19 +01:00
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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2019-05-10 15:52:00 +02:00
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// Mainboard specific
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#include "acpi/mainboard.asl"
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}
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