2020-04-04 18:51:11 +02:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2015-07-31 11:10:46 +02:00
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2019-03-03 07:01:05 +01:00
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#include <device/mmio.h>
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2015-07-31 11:10:46 +02:00
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#include <console/console.h>
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#include <soc/wdt.h>
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2016-03-24 00:08:11 +01:00
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#include <vendorcode/google/chromeos/chromeos.h>
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2015-07-31 11:10:46 +02:00
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int mtk_wdt_init(void)
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{
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uint32_t wdt_sta;
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2021-04-22 07:34:04 +02:00
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/* Writing mode register will clear status register */
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2018-06-12 08:10:09 +02:00
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wdt_sta = read32(&mtk_wdt->wdt_status);
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2015-07-31 11:10:46 +02:00
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2021-04-22 07:34:04 +02:00
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if (CONFIG(CLEAR_WDT_MODE_REG))
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write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS);
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2015-07-31 11:10:46 +02:00
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printk(BIOS_INFO, "WDT: Last reset was ");
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2016-03-24 00:08:11 +01:00
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if (wdt_sta & MTK_WDT_STA_HW_RST) {
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2015-07-31 11:10:46 +02:00
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printk(BIOS_INFO, "hardware watchdog\n");
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2016-03-24 00:08:11 +01:00
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mark_watchdog_tombstone();
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} else if (wdt_sta & MTK_WDT_STA_SW_RST)
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2015-07-31 11:10:46 +02:00
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printk(BIOS_INFO, "normal software reboot\n");
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else if (wdt_sta & MTK_WDT_STA_SPM_RST)
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printk(BIOS_INFO, "SPM reboot\n");
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else if (!wdt_sta)
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printk(BIOS_INFO, "cold boot\n");
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else
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printk(BIOS_INFO, "unexpected reset type: %#.8x\n", wdt_sta);
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/* Config watchdog reboot mode:
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* Clearing bits:
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* DUAL_MODE & IRQ: trigger reset instead of irq then reset.
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* EXT_POL: select watchdog output signal as active low.
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* ENABLE: disable watchdog on initialization.
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* Setting bit EXTEN to enable watchdog output.
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*/
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2019-12-03 07:03:27 +01:00
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clrsetbits32(&mtk_wdt->wdt_mode,
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MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ |
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MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE,
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MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
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2015-07-31 11:10:46 +02:00
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return wdt_sta;
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}
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