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coreboot-kgpe-d16/src/soc/amd/stoneyridge/smihandler.c

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soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
/*
amd/stoneyridge: Refactor SMI handler Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-29 01:21:09 +02:00
* This file is part of the coreboot project.
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
*
amd/stoneyridge: Refactor SMI handler Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-29 01:21:09 +02:00
* Copyright (C) 2017 Advanced Micro Devices, Inc.
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
* Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
amd/stoneyridge: Refactor SMI handler Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-29 01:21:09 +02:00
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
*/
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <delay.h>
#include <soc/smi.h>
stoneyridge: Rename hudson to southbridge Simplify funciton names and remove reference to hudson in stoneyridge. The southbridge in Stoney Ridge is Kern and hudson naming is no longer accurate. BUG=b:62200157 BRANCH=none TEST=Build and booted on Kahlee. Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20912 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-08 03:08:24 +02:00
#include <soc/southbridge.h>
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
stoneyridge: Rename hudson to southbridge Simplify funciton names and remove reference to hudson in stoneyridge. The southbridge in Stoney Ridge is Kern and hudson naming is no longer accurate. BUG=b:62200157 BRANCH=none TEST=Build and booted on Kahlee. Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20912 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-08 03:08:24 +02:00
static void sb_apmc_smi_handler(void)
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
{
u32 reg32;
amd/stoneyridge: Check SMI command address before reading Use the currently programmed address of the SMI command port before checking the passed command. This ensures we're reading the right port in case the port was relocated without our knowledge. Change-Id: I8a3ca285d3a9afd4a107cd471c202abf03f372ac Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27 21:32:38 +02:00
const uint8_t cmd = inb(pm_acpi_smi_cmd_port());
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
switch (cmd) {
amd/stoneyridge: Use generic SMM command port values Remove the old Hudson-specific SMM command port definitions and use the ones in cpu/x86/smm.h. Change-Id: I3de9a178e5f189ac1dbc921e41b69d47e3796a4f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22 23:14:46 +02:00
case APM_CNT_ACPI_ENABLE:
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
reg32 = inl(ACPI_PM1_CNT_BLK);
reg32 |= (1 << 0); /* SCI_EN */
outl(reg32, ACPI_PM1_CNT_BLK);
break;
amd/stoneyridge: Use generic SMM command port values Remove the old Hudson-specific SMM command port definitions and use the ones in cpu/x86/smm.h. Change-Id: I3de9a178e5f189ac1dbc921e41b69d47e3796a4f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22 23:14:46 +02:00
case APM_CNT_ACPI_DISABLE:
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
reg32 = inl(ACPI_PM1_CNT_BLK);
reg32 &= ~(1 << 0); /* clear SCI_EN */
outl(ACPI_PM1_CNT_BLK, reg32);
break;
}
mainboard_smi_apmc(cmd);
}
int southbridge_io_trap_handler(int smif)
{
return 0;
}
amd/stoneyridge: Refactor SMI handler Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-29 01:21:09 +02:00
/*
* Table of functions supported in the SMI handler. Note that SMI source setup
* in southbridge.c is unrelated to this list.
*/
struct smi_sources_t smi_sources[] = {
{ .type = SMITYPE_SMI_CMD_PORT, .handler = sb_apmc_smi_handler },
};
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
static void process_smi_sci(void)
{
amd/stoneyridge: Clean up smihandler.c Replace hardcoded values with defined ones. Change-Id: Ic72a51516a1763b2380e60397f5a3aeb32457b65 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-26 22:52:45 +02:00
const uint32_t status = smi_read32(SMI_SCI_STATUS);
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
/* Clear events to prevent re-entering SMI if event isn't handled */
amd/stoneyridge: Clean up smihandler.c Replace hardcoded values with defined ones. Change-Id: Ic72a51516a1763b2380e60397f5a3aeb32457b65 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-26 22:52:45 +02:00
smi_write32(SMI_SCI_STATUS, status);
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
}
amd/stoneyridge: Refactor SMI handler Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-29 01:21:09 +02:00
static void *get_source_handler(int source)
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
{
amd/stoneyridge: Refactor SMI handler Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-29 01:21:09 +02:00
int i;
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
amd/stoneyridge: Refactor SMI handler Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-29 01:21:09 +02:00
for (i = 0 ; i < ARRAY_SIZE(smi_sources) ; i++)
if (smi_sources[i].type == source)
return smi_sources[i].handler;
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
amd/stoneyridge: Refactor SMI handler Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-29 01:21:09 +02:00
return NULL;
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
}
amd/stoneyridge: Refactor SMI handler Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-29 01:21:09 +02:00
static void process_smi_sources(uint32_t reg)
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
{
amd/stoneyridge: Refactor SMI handler Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-29 01:21:09 +02:00
const uint32_t status = smi_read32(reg);
int bit_zero = 32 / sizeof(uint32_t) * (reg - SMI_REG_SMISTS0);
void (*source_handler)(void);
int i;
for (i = 0 ; i < 32 ; i++) {
if (status & (1 << i)) {
source_handler = get_source_handler(i + bit_zero);
if (source_handler)
source_handler();
}
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
}
amd/stoneyridge: Refactor SMI handler Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-29 01:21:09 +02:00
if (reg == SMI_REG_SMISTS0)
if (status & GEVENT_MASK)
/* Gevent[23:0] are assumed to be mainboard-specific */
mainboard_smi_gpi(status & GEVENT_MASK);
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
amd/stoneyridge: Refactor SMI handler Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-29 01:21:09 +02:00
/* Clear all events in this register */
smi_write32(reg, status);
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
}
amd/stoneyridge: Enable SMM in TSEG Add necessary features to allow mp_init_with_smm() to install and relocate an SMM handler. SMM region functions are added to easily identify the SMM attributes. Adjust the neighboring cbmem_top() rounding downward to better reflect the default TSEG size. Add relocation attributes to be set by each core a relocation handler. Modify the definition of smi_southbridge_handler() to match TSEG prototype. BUG=b:62103112 Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-14 01:47:31 +02:00
void southbridge_smi_handler(void)
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
{
amd/stoneyridge: Clean up smihandler.c Replace hardcoded values with defined ones. Change-Id: Ic72a51516a1763b2380e60397f5a3aeb32457b65 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-26 22:52:45 +02:00
const uint16_t smi_src = smi_read16(SMI_REG_POINTER);
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
amd/stoneyridge: Clean up smihandler.c Replace hardcoded values with defined ones. Change-Id: Ic72a51516a1763b2380e60397f5a3aeb32457b65 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-26 22:52:45 +02:00
if (smi_src & SMI_STATUS_SRC_SCI)
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
process_smi_sci();
amd/stoneyridge: Clean up smihandler.c Replace hardcoded values with defined ones. Change-Id: Ic72a51516a1763b2380e60397f5a3aeb32457b65 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-26 22:52:45 +02:00
if (smi_src & SMI_STATUS_SRC_0)
amd/stoneyridge: Refactor SMI handler Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-29 01:21:09 +02:00
process_smi_sources(SMI_REG_SMISTS0);
amd/stoneyridge: Clean up smihandler.c Replace hardcoded values with defined ones. Change-Id: Ic72a51516a1763b2380e60397f5a3aeb32457b65 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-26 22:52:45 +02:00
if (smi_src & SMI_STATUS_SRC_1)
amd/stoneyridge: Refactor SMI handler Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-29 01:21:09 +02:00
process_smi_sources(SMI_REG_SMISTS1);
amd/stoneyridge: Clean up smihandler.c Replace hardcoded values with defined ones. Change-Id: Ic72a51516a1763b2380e60397f5a3aeb32457b65 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-26 22:52:45 +02:00
if (smi_src & SMI_STATUS_SRC_2)
amd/stoneyridge: Refactor SMI handler Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-29 01:21:09 +02:00
process_smi_sources(SMI_REG_SMISTS2);
amd/stoneyridge: Clean up smihandler.c Replace hardcoded values with defined ones. Change-Id: Ic72a51516a1763b2380e60397f5a3aeb32457b65 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-26 22:52:45 +02:00
if (smi_src & SMI_STATUS_SRC_3)
amd/stoneyridge: Refactor SMI handler Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-29 01:21:09 +02:00
process_smi_sources(SMI_REG_SMISTS3);
amd/stoneyridge: Clean up smihandler.c Replace hardcoded values with defined ones. Change-Id: Ic72a51516a1763b2380e60397f5a3aeb32457b65 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-26 22:52:45 +02:00
if (smi_src & SMI_STATUS_SRC_4)
amd/stoneyridge: Refactor SMI handler Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-29 01:21:09 +02:00
process_smi_sources(SMI_REG_SMISTS4);
soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05 05:17:45 +02:00
}
void southbridge_smi_set_eos(void)
{
uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
reg |= SMITRG0_EOS;
smi_write32(SMI_REG_SMITRIG0, reg);
}
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