coreboot-kgpe-d16/src/mainboard/emulation/spike-riscv/Kconfig.name

config BOARD_EMULATION_SPIKE_UCB_RISCV
	bool "SPIKE ucb riscv"
riscv-spike: support for Spike emulation of riscv Spike support: QEMU RISCV is broken, and the maintainers at Berkeley are working on it, but at the moment spike is the only way to test on riscv. Add support for spike console output for debugging. Privileged ISA: Update to privileged ISA in RISCV (machine, supervisor, hypervisor, user modes) broke exisitng RISCV asm, and bootblock.S was updated to match the new spec. Clean old assembly [pg: things build with gcc 4.9 now, but don't expect them to work. Hardcoding register names into the assembler language may not be the smartest idea of the RISCV folks.] Change-Id: Ie2c109d3c26712c207512f74f28ce1a925e6e181 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11078 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> 2015-07-30 02:43:20 +02:00			`config BOARD_EMULATION_SPIKE_UCB_RISCV`
			`bool "SPIKE ucb riscv"`