2015-05-13 03:19:47 +02:00
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config SOC_INTEL_SKYLAKE
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bool
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help
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Intel Skylake support
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if SOC_INTEL_SKYLAKE
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_RAMSTAGE_X86_32
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2015-05-13 03:23:27 +02:00
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select ARCH_ROMSTAGE_X86_32
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select ARCH_VERSTAGE_X86_32
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2015-05-13 03:19:47 +02:00
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select BACKUP_DEFAULT_SMM_REGION
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select CACHE_MRC_SETTINGS
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2015-08-30 05:00:24 +02:00
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
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2015-05-13 03:19:47 +02:00
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select COLLECT_TIMESTAMPS
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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2015-07-24 20:00:36 +02:00
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select GENERIC_GPIO_LIB
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2015-05-13 03:23:27 +02:00
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select HAS_PRECBMEM_TIMESTAMP_REGION
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select HAVE_HARD_RESET
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2015-07-30 20:41:01 +02:00
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select HAVE_INTEL_FIRMWARE
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2015-05-13 03:19:47 +02:00
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select HAVE_MONOTONIC_TIMER
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select HAVE_SMI_HANDLER
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select IOAPIC
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select MMCONF_SUPPORT
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select MMCONF_SUPPORT_DEFAULT
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select PARALLEL_MP
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select PCIEXP_ASPM
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select PCIEXP_COMMON_CLOCK
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select PCIEXP_CLK_PM
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2015-07-13 20:50:34 +02:00
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select PCIEXP_L1_SUB_STATE
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2015-05-13 03:23:27 +02:00
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select PLATFORM_USES_FSP1_1
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select REG_SCRIPT
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select RELOCATABLE_MODULES
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select RELOCATABLE_RAMSTAGE
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select SOC_INTEL_COMMON
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2015-09-09 01:12:44 +02:00
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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2015-05-13 03:23:27 +02:00
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select SOC_INTEL_COMMON_RESET
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2015-05-13 03:19:47 +02:00
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select SMM_TSEG
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select SMP
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select SPI_FLASH
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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select TSC_CONSTANT_RATE
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select TSC_SYNC_MFENCE
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select UDELAY_TSC
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2015-05-13 03:23:27 +02:00
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select USE_GENERIC_FSP_CAR_INC
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2015-05-13 03:19:47 +02:00
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config BOOTBLOCK_CPU_INIT
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string
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default "soc/intel/skylake/bootblock/cpu.c"
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config BOOTBLOCK_NORTHBRIDGE_INIT
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string
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default "soc/intel/skylake/bootblock/systemagent.c"
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2015-05-13 03:23:27 +02:00
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config BOOTBLOCK_RESETS
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2015-05-13 03:19:47 +02:00
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string
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2015-05-13 03:23:27 +02:00
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default "soc/intel/common/reset.c"
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2015-05-13 03:19:47 +02:00
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2015-05-13 03:23:27 +02:00
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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2015-05-13 03:19:47 +02:00
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string
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2015-05-13 03:23:27 +02:00
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default "soc/intel/skylake/bootblock/pch.c"
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2015-05-13 03:19:47 +02:00
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2015-05-13 03:23:27 +02:00
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config CPU_ADDR_BITS
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int
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default 36
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2015-05-13 03:19:47 +02:00
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2015-05-13 03:23:27 +02:00
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config DCACHE_RAM_BASE
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hex "Base address of cache-as-RAM"
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default 0xfef00000
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2015-05-13 03:19:47 +02:00
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2015-05-13 03:23:27 +02:00
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config DCACHE_RAM_SIZE
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hex "Length in bytes of cache-as-RAM"
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2015-09-16 21:27:26 +02:00
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default 0x10000
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2015-05-13 03:19:47 +02:00
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help
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2015-05-13 03:23:27 +02:00
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The size of the cache-as-ram region required during bootblock
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and/or romstage.
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2015-05-13 03:19:47 +02:00
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2015-05-13 03:23:27 +02:00
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config HEAP_SIZE
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hex
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default 0x80000
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config IED_REGION_SIZE
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hex
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default 0x400000
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config MMCONF_BASE_ADDRESS
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hex "MMIO Base Address"
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default 0xe0000000
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config MONOTONIC_TIMER_MSR
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def_bool y
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select HAVE_MONOTONIC_TIMER
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help
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Provide a monotonic timer using the 24MHz MSR counter.
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config PRE_GRAPHICS_DELAY
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int "Graphics initialization delay in ms"
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default 0
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help
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On some systems, coreboot boots so fast that connected monitors
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(mostly TVs) won't be able to wake up fast enough to talk to the
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VBIOS. On those systems we need to wait for a bit before executing
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the VBIOS.
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config SERIAL_CPU_INIT
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bool
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2015-05-13 03:19:47 +02:00
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default n
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2015-05-13 03:23:27 +02:00
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config SERIRQ_CONTINUOUS_MODE
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bool
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2015-09-10 02:22:09 +02:00
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default n
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2015-05-13 03:19:47 +02:00
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help
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2015-05-13 03:23:27 +02:00
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If you set this option to y, the serial IRQ machine will be
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operated in continuous mode.
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config SMM_RESERVED_SIZE
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hex
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default 0x200000
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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config VGA_BIOS_ID
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string
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default "8086,0406"
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2015-05-13 03:19:47 +02:00
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2015-07-30 23:52:56 +02:00
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config UART_DEBUG
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bool "Enable UART debug port."
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default n
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2015-08-16 01:36:15 +02:00
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select CONSOLE_SERIAL
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2015-07-30 23:52:56 +02:00
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select DRIVERS_UART
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select DRIVERS_UART_8250MEM_32
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2015-09-03 07:41:29 +02:00
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config CHIPSET_BOOTBLOCK_INCLUDE
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string
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default "soc/intel/skylake/bootblock/timestamp.inc"
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2015-05-13 03:19:47 +02:00
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endif
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